SU1164723A1 - Processor for digital computer - Google Patents

Abstract

DIGITAL COMPUTER MACHINE PROCESSOR, containing arithmetic logic unit, control device, memory, register unit, first and second operand selectors, and result selector, the output of which is connected to the first input of the register unit, the first and second groups of outputs of which are connected to the first selector inputs and second operands, respectively, whose outputs are connected to the first and second inputs of the arithmetic logic unit, respectively, whose outputs are connected respectively the result selector input group, the address output of the reg-unit, the gistra is connected to the memory input address, the output of which is connected to the second input of the register unit and the control system code input, the clock input of which is the processor clock input, the outputs of the control unit Jj3 are connected respectively, with the control inputs of the arithmetic logic unit, the block of registers, the selectors of the first and second operands, and the result selector, with the synchronizing input of the block of registers and from the input The memory accessing and writing of the memory device is different from the fact that, in order to expand its functionality by normalizing fixed numbers, a normalization register, comparison elements, a condition decoder and a zero decoder are entered, and the output of the selector the first operand is connected to the input of the register of normalization, the output of which is directly connected to the third input of the result selector and through the first comparison element to the first input of the condition decoder, the second and third inputs of which respectively, the second element is connected by comparing the zero decoder with the output of the selector of the first operand 05 and the information input of the memory to the device, the output of the condition decoder is connected to the input of the control unit, the corresponding outputs of which are O9 connected to the control inputs of the normalization register and the condition decoder, the fourth input of which is connected with the clock input of the processor, and the output of the sum of the arithmetic logic unit is connected to the third input of the block of registers.

Description

The invention relates to computing technology and may be used to construct central processing units of digital computing machines. .

The aim of the invention is to enhance the functionality of the processor by normalizing fixed-point numbers.

FIG. 1 shows a block diagram of a processor; in fig. 2 control circuit diagram; in fig. 3 is a block diagram of the registers of FIG. 4; a normalization register; in fig. 5 is a controlled descrambler circuit; in fig. 6 shows a condition decoder circuit; in fig. 7 is a diagram of a write decoder

The processor contains an arithmetic logic unit 1, a control unit 2, a storage device 3, a register block 4, a normalization register 5, a condition decoder 6, a first operand selector 7, a second operand selector 8, a result selector 9, a decoder 10 zero, elements 1 I and 12 comparisons. The processor clock input 13 is connected to the clock inputs of the control device 2 and the fourth input of the decoder 6 conditions. Control device 2 has outputs I4-26.

Control device 2 (Fig. 2) contains r shift control registers 27, shift register 28, controlled by decoder 29, register 30, write decoder 31, triggers 32 and 33, element OR-HE 34, p elements And 35, p elements And 36, (t + 2) elements And 37, elements And 38-45, elements OR 46-58, q elements OR 59, element And 60, and three elements NOT 61 (61

Block 4 registers (Fig. 3) contains the address register 62, information register 63, m registers 64 General purpose, the counter 65 commands and the switch 66...

Register 5 normalization (Fig. 4) contains n triggers 67, p-2 elements foB AND-OR 6B, elements And 69 and 70 and inverter 71.

Managed decoder 29 (Fig. 5 contains n elements, IM 72, n elements And 73, n elements And 74, iverter 75, buffer register 76 of the opcode and decoder 77 of the opcode.

The decoder 6 conditions (Fig. 6) contains the trigger 7.8, the switch 79, the element OR 80 and the inverter 81. The descriptor 31 of the record (Fig. 7) contains the descriptor 82, the p elements AND-OR 83 and the inverter 84.

The processor of the specialized computer operates when the normalization of the fixed-number number is performed as follows.

Before performing normalization, the operand is located in general register 64t. In the last cycle of the execution of the | | one command from the last bit of the corresponding control shift register 27, the signal goes to the output of the OR 5B element. From the output of the element OR 58, the signal through the element 56 enters the control inputs of the general-purpose register 64, the switch 66, and the input of the advance of the command counter 65 ,. the switch is configured to feed to the address input of the storage device 3 of the contents of general register 64 (the address of the control word), the command counter 65 increments the command address code, and the general purpose register 64 is configured to receive a code from the second input connected to the counter output 65 teams. In addition, the signal from the output of the element OR 58 through the element OR 46 is fed to the input of the treatment. memory 3, the command word from the output of which enters the code input, control device 2, the field of indication of the address of the control word enters the inputs of the trigger 32 and element 44, the operation code field enters the input of the controlled decoder 29, and the field R and R2 of the control word is fed to the input of register 30. At the end of the cycle, when an and aIyca appears on the clock frequency bus 13, the advanced value of the command counter 65 is written to the register 6i4 | general purpose signal received from the output of the element AND 42 through the element OR 48 to the register synchronizing input. 64J General Purpose.

If the next command word is to be executed in the RR format (zero bit of the addressing attribute), the AND 44 element is closed, there is no signal at its output, and the signals from the element outputs. OR 58 and the inverter 75 open the AND 74f–74 elements in the controlled decoder 29 and the operation code through elements AND 74, - 74p, elements OR 72 - 72 are fed to the input of the decoder 77 CO of the operation, at the last output of which, if the operation code corresponds to the command of normalizing the number with a fixed comma, is the signal AND is input to the shift The control register 27 and the clock frequency pulse transmitted through the element I 40 to the synchronization input of the dual register 27 (the control switches on its first bit (the element 40 oT is closed for the pulse and clock frequency). element output 43 is absent, and NOT 61 is present at the output of the element.) At the same time, since element 39 is opened by the signal from the output of the element OR 58 by a clock frequency pulse generating a signal at the output of the element 39, the value of the sign of addressing the write to trigger 32, the value of the fields R1 and R2 h pisyvaets in the register 30 and the value of the opcode with a zapishett bufernsh operational code register 76, tion. In addition, in the same cycle, a single signal is pushed out of the last bit of the shift control register 21, which was previously turned on and provided the output signal of the OR element 58, after which the first cycle of the normalization command is started. If the addressing field in the selected command word points to RX mode, not RR (one in the addressing attribute field), then the described process repeats with the only difference that trigger one records in trigger 32 and output signal AND 44 is present. , which prohibits the passage of an operation code through AND 74 - 74 elements (a command with a zero operation code is absent in the command system), therefore, the clock pulse does not include the first control shift register 27, but the first time the shift register number 28. The register 28 provides sampling the second operand in RX mode for other commands from the command system and preparing the executive address for the command to normalize the fixed-point number, which has one operand and two results. At the same time, in the first execution mode of sampling the second operand in the RX mode, the F signal from the output of the first bit of the shift register 28 through the OR 56 element feeds to the address input of the memory device 3 the offset address code from the register 64, general purpose (in the RX mode the command word occupies two adjacent cells in the memory), and through the OR 46 element it receives the memory access signal CK) to the device 3. The offset from the output of the memory device 3 is fed to the second input of the information register 63 in block 4 of registers, which is sign The Pf ale, accessed via the OR 50 element, the output 22 of the control device 2 for controlling the input of the information register 63, is configured to receive information from its second input. The signal F is fed through the input to the element 37. At the end of this cycle, a pulse is transmitted from the clock frequency 13 of the processor to the clock input of the information register 63, to which the offset is written. On the same clock pulse, a single signal advances from the first to the second bit of the shift register 28, -which produces a signal F-. In the second cycle of the sampling mode of the second operand, the modification is performed by summing the offset with an index, which is 64j total, found in the register specified by the R-2 field of the value, mandaln. The code j in the field R2 of register 30, entering through the open elements I 35, -35p, the output 26 of the control device 2 to the control input of the selector 8 of the second operand, provides the contents of the general-purpose register 64 j; the second input of the arithmetic logic unit J. Since the output of the OR-NOT 34 element has an E signal, the AND elements are closed and the output of the selector 7 of the first operand is not sent to the general register 64j indicated by the field R in register 30, but the information register 63, which O9s. stumbles on the first input of the orientological device 1. The signal F, through the elements OR 55 and 53, the outputs 15 and 17 of the control device 2, proceeds to the first and third control inputs of the arithmetic logic. devices 1, which serve respectively for supplying a direct code of the first and second operands, while the output of the sum of the arithmetic logic unit I is the executive address (sum of offset and index), which through the third input of block 4 of registers arrives on. the input of the address register 62. In addition, the signal Fj permits the passage of a clock frequency pulse through the AND element to the synchronization input of the address register 62 and the writing of the executive address into it. By the same clock pulse, a single signal is moved from the second to the third bit of the shift register 28, which produces the signal Fj .. 38 to the third cycle of the second operand sampling mode in the RX mode, which has no meaning for other commands from the command system), the address input of the storage device is fed to the contents of the address register 62, since there is no signal at the control input of the switch 66. Through the IDI element 46, the signal Fj is fed to the reversal input of device 3, from the output of which the code of the second operand arrives at the second input of block 4 of registers and the second input of information register 63. In addition, the signal F through the element OR 50, output 22 of device 2 control enters the control input of the information register 63 and sets it to receive information from its second input. The signal F through the element OR 49, arriving at the input of the element AND 37, once solves the passage of a clock frequency pulse to the synchronizing input of the information register 63, into which the second operand is written. When a signal F, J appears at the output of the element HE 61 | There is no signal at the input of the trigger 33, so a zero is written to the trigger 33, which, during the research institute of the first cycle of execution of any command, provides the second operand (instead of supplying the index from jpH 11 3 general 641). In addition to J -,. In addition, the signal F, to the third control input of the controllable decoder 29, provides the operation code from the buffer register 76 through the operation elements 73, -73 ',. elements SHS to the input of the operation code decoder 77, and with the operation code corresponding to the normalization command, the clock signal received through AND 40 to the clock input of the shift register 27 of the control frequency records a single signal at its first speed, after which the actual signal begins execution of the command to normalize the number with a fixed comma. Normalization of a fixed-point number Produced as follows,. In the first, command execution cycle at the output of the shearing array 27, the signal A is generated. The output i code-field R1 of the register 30 through the elements And, the output 25 of the control unit 2 enters the control input of the selector 7 of the first operand and tunes it to pass to its output of the contents of the register 64, general purpose. The number from the output of the selector 7 of the first operand is fed to the inputs of the comparison element 11, the decoder 10 zero and to the information input of the normalization register 5, the control input 21 of which has no signal, so this number goes to the trigger inputs 67.-67 ". Comparison element II generates a signal at its output, when the digit bit of the number is unequal, to the oldest bit of the mantissa number (the number is normalized), and the 10 zero decoder produces a .i signal at its bypass when the number is zero (the number is normalized). Thus, at the output of the element OR 80 and, accordingly, at the first input of the switch 79, a signal is generated if the number is normalized, and there is no signal if the number needs to be normalized. The signal through the output 19 of the control unit 2 is fed to the control input of the decoder 6 CONDITION and sets the switch 79 to pass the signal from its first input, through the inverter .81 to the trigger input 78. The processor clock pulse from the clock input 13 of the processor records the signal value from the output of the inverter 81 to the trigger 78. In addition, the normalized number of the same pulse transmitted through the element 41, opened at the first input by signal A, (passed through the element OR 51), through the output 20 of the control device 2 to the synchronization input of the register normalization country 5, is recorded in the triggers 67) 67 (in the absence of a signal at the output 21 of the control device 2, the element 70 is open for synchronization) The signal Af coming through the element OR 49 at the input of the element I permits the passage of the pulse clock frequency to the synchronizing input of the information register 63, which, the absence of a signal at the control input is configured to record information from its first input connected to the third input of the register unit and with the output of the sum of the arithmetic unit I. The first, second, third and fourth control inputs of the arithmetic logic unit 1 serve respectively for supplying the first operand with a direct transfer job code in small shy discharge arithmetic logic unit I of the second operand supplying direct feed code and inverse code of the second operand. Since the signals at the control inputs of the arithmetic logic unit I in the first cycle of execution of the normalization command are absent at the output of the sum of the arithmetic logic unit I there is a left-hand code, which is written to the information register 63. In addition, the clock pulse, arrival through element AND 40 to the synchronizing input of the shift register 27j of control, moves a single signal from its first bit to its second bit and produces: a signal, AL, which determines the second cycle of the command normalization. If the initial number is normalized, then after the first cycle of executing the command, the signal at the output of the decoder 6 conditions, the additional input of the control unit 2 and the input of the And 43 element is absent, therefore when a pulse is generated at the clock input 13 of the processor, the signal to the clock inputs of the normalization register 5 and the information register 63 does not arrive and these registers do not change its state. The absence of a signal at the output of the element And 43 opens the element And 40, and the clock pulse moves the single signal from the second to the third bit of the shift register 27 control. In doing so, the contents of the normalization register 5 is written to the general register 64 in the manner described below. If the original number is not normal. After the first cycle of executing the command-and, respectively, the signal is present at the first input of the AND element 43, the second cycle of executing the command proceeds in the following way. The signal Aj arriving at the input of the OR-NOT 34 element, produces a zero code at the outputs of the AND elements, which provides the output of the selector 7 of the first operand and, accordingly, to the first input of the arithmetic logic unit 1, the contents of the information register 63. This same signal A, passing through the elements OR 55 and 54 and the outputs 15 and 16 of the control unit 2 to the first and second control inputs of the arithmetic logic unit I, provides the output of the sum of the arithmetic logic unit I of the enlarged units in the lower bit of the contents of the information register 63, In addition, the signal Ag, passed through the element OR 57, opens the element And 45. The same signal A2, passes through the element And 43 first, enters through the output 21 of the control unit 2 and the reference signal the input of register 5 normalization and. prohibits the triggering of the element 70 and the passage of information to the input of flip-flops 672--67, from the information input of the register 5 normalization and allows the input to the input of flip-flops 67j 67fj. information from the right (as shown in the diagram) triggers 67 ,, - 67. In the second, passing through the SHSh 51 element, the signal from the output of the AND 43 element opens the AND 41 element. Third, passing through the OR 49 element, the signal opens the AND 37fn + i element Fourth, passing through the HE 6 element, the signal prohibits triggering element 40 and, accordingly, the promotion of a single signal in the shift register 27 (control.

In addition, the absence of a signal at the output 19 of the control unit 2 configures the switch 79 to pass the signal from the output of the element 12, the comparison through the second input of the switch 5 of the torus 79, the inverter 81 to the input of the trigger 78. The element 12 compares the sign of the bit and the bit following after the higher bit of the mantissa, the numbers in register 5 of normalization 10 (outputs of flip-flops 67j and 67 in register 5 of normalization) and work similarly to the comparison element 1. When a pulse arrives on the bus 13 of the clock frequency, the shift register15 27 {control does not change its state; in register 5 of normalization, the mantissa is shifted to the left by one bit (the last bit is filled with zero), increased by 20 units. 63 from the output of the sum of the arithmetic unit 1 is recorded in the information register 63, and the pre-trust (not shifted) number of 25

register 5 normalization is recorded in general register 64, since the code from the output of the field R1 of register 30 through the decoder 31 records opens the element 37 which passes the JQ clock pulse from the output of the element 45 to the synchronization input of the register 64, while the signal Aj is supplied only on those inputs of the elements OR 59 59t (marked A in the drawing), so that

The outputs (output 14 of the control unit 2) have generated a code that provides the output to the output of the selector 9 of the result and, respectively, on the input. dies of general purpose registers 64 of register 5 normalization through its third input.

If after the shift in the second cycle I. . . the number will become normalized in trig-45

At the end of the pulse, the frequency 78 will record a zero signal and it will go from the output of the decoder 6 to the auxiliary input of control device 2, after which the 50th cycle (determined by outputting the signal Ag to the output of the control shift register 27) It is similar to the execution of the second cycle with a normalized initial value of the number, 55 with the general-purpose register 64 being written with the normalized number. If after performed

No second cycle number is normalizo | 3ano,. then the second cycle in the shift mode of the contents of the register 5 normalization is repeated. Thus, the second cycle is repeated (K + I) times when the normalization command is executed, where K is the shift constant during normalization, indicating the number of shifts in the mantissa (one bit at each shift) during normalization. The shift constant K at normalization is formed in the information register 63. With a zero signal at the output of the decoder 6 conditions, the second cycle of the normalization command is executed one last time, after which the single signal moves from the second bit to the third bit of the shift register 27 (control, which generates a signal. And, and begins the execution of the third cycle.

In the third cycle of the normalization command, the second result is written (the shift constant in the memory, at that, the signal Aj arrives at the input of the OR-NOT 34 element and produces a zero code at the outputs of the AND elements, in which the contents of the information register 63 is fed to the output of the selector 7 of the first operand and, accordingly, the first information input of the storage device 3. The Ah signal, which is fed to the control input of the record decoder 3, supplies the code j from the output of the R2 field of the register 30 to the input of the decoder 82, the signal from the output of which opens the element AND 37, |. In addition, the signal A 5 through the element OR 55, the output 15 of the control device 2, arriving at the first control input of the arithmetic logic unit 1, provides the shift constant to the output of the sum arithmetic -logical device 1. In addition, the signal AZ is fed to the inputs of those elements OR 594-59 (shown in the drawing Ap), which is at their outputs and, respectively, at the control input of the result selector 9 to generate a code that provides content from the output su - we are ari ethical logical device 1 to output the result selector 9 and the input 64 general purpose registers.

If the normalization command is executed in the RR mode (low potential 11 at the output of the trigger 32), then the signal A passes through element AND 60, element OR 57 and opens element 1 and 45, while the clock frequency pulse from the bus 13 clock frequency passes through element AND 45, element I 37; The sync input of general-purpose register 64 "sat- writes the shift constant to it. If the command is executed in the mode: IU RX (high potential at the output of the trigger 32), then the signal AZ through the element 38, through the elements 18 and 47 enters the inversion input and the recording input of the memory 3, and the shift constant is written memory 3 at the executive address ,. The stored -312 schmus is located in address register 62 and sent via switch 66 to address input of memory 3. Thereafter, a single signal from the clock pulse moves from the third to fourth bit of the shift register 274, which the signal A generates, providing, as described in section 3, development of the next command word. When executing other commands from the system of commands, the corresponding-shift control registers 27 are included, which generate signals at their outputs, with the help of which corresponding micro operations at the outputs of control devices 2 are generated.

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Figm

Claims (1)

A DIGITAL COMPUTER MACHINE PROCESSOR, containing arithmetic — logic — a control device, a memory device, a register block, selectors of the first and second operands, and a result selector whose output is connected to the first input of the register block, the first and second groups of outputs of which are connected to the inputs selectors of the first and second operands, respectively, whose outputs are connected respectively to the first and second inputs of the arithmetic-diagnostic device a, the outputs of which are connected respectively to Rupp result selector inputs, the address output unit D · -, giste connected to the address input of the memory device, the output of which is connected to the second input of the register block and a code input of the control device, whose clock input is a clock input of processor, outputs control device.. are connected respectively to the control inputs of the arithmetic-logic device, register block, selectors of the first and second operands and the result selector, with a synchronizing input of the register block and with the access and write inputs of the storage device, which requires that, in order to expand the functionality by normalizing numbers with fixed .zapyatoy, it introduced normalization register, comparison elements and decoder descrambler conditions zero, the output selector _Λ is coupled to the first operand WMOs ohm 5 of the normalization register, the output of which is connected directly to the third input of the result selector and through the first element of comparison to the first input of the condition decoder, the second and third inputs of which are connected respectively through the second element by comparisons of the zero decoder with the output of the selector of the first operand and the information input of the storage device , the output of the condition decoder is connected to the input of the control device, the corresponding outputs of which are connected to the control inputs of the normalization register and the decoder conditions of the torus, a fourth input coupled to a clock input of the processor, and the output sum arithmetic logic unit is coupled to the third input register block. 1 1164723 2