SU1661808A1 - Image characters separator - Google Patents

Abstract

The invention relates to automation and computing and is intended for optical image analyzers. The aim of the invention is to improve the accuracy of the device. The device contains photoreceiving elements, decision blocks, a display unit, a control unit, a linearly varying voltage generator, a reference voltage source, and a gain unit. The decision block contains a gated comparator, three switches, two memory elements, an AND element, a modulo two. Due to the halftone processing, a high accuracy of the device is achieved. 1 hp f-ly, 5 ill.

Description

The invention relates to automation and computing and can be used as part of optical image analyzers.

The purpose of the invention is to improve the accuracy of the device.

FIG. 1 shows a block diagram of the device; Fig. 2 illustrates the matrix organization of the device; FIG. 3 shows the electrical circuit of the decision block; 4 is the electrical circuit diagram of the control unit; figure 5 is a temporary diagram of the operation of the device. The feature for selecting features (areas of equal intensity) of images (Fig. 1) contains a matrix of photodetector elements 1 whose optical inputs are information inputs of the device, display unit 2 — a matrix of electro-optical converters whose optical outputs are optical outputs of the device, a matrix of decision blocks 3, generator 4 linear

variable voltage (clay), control unit 5, reference voltage source 6. The first Ui, the second Ua, the third Oz, the fourth 1M, the fifth Us outputs of the control unit 5 are connected to the corresponding control inputs of the decision units 3. The sixth output Ue of the control unit 5 is connected to the clock input of the generator 4 linearly varying voltage. The output E of the source 6 of the reference voltage is connected to the seventh control inputs of the decision blocks 3. The blocks are connected via a common bus 7.

Each photodetector element 1 is loaded onto a gain unit 8 (analog amplifier). The matrix of electro-optical converters of the display unit 2 may be similar to that used in pictographic digital computers. The range of variation of the output voltage of generator 4 must correspond to the range of image intensities. The source 6 of the reference voltage can be any secured

with

oh oh

00

about

00

a voltage level of 1 at its output.

The matrix organization of the device (Fig. 2) consists of separate decisive blocks 3 arranged in a matrix, the information inputs of which are connected through amplification blocks 8 to the outputs of the corresponding photoreceiver elements 1, and information outputs to the inputs of the corresponding display blocks 2 (electro-optical converters). Each of the decision blocks 3 has seven control inputs: the first Ui, the second U2, the third Uz, the fourth LM, the fifth Us, the sixth 1) mission, the seventh E. The connection of the decision blocks 3 with the common bus 7 is carried out using internal buses 9.

The decision unit 3 (FIG. 3) contains a gated comparator 10, the first 11, the second 12 and the third 13 switches, the first 14 and the second 15 memory elements, an adder 16 modulo two, the AND element 17. The information input of the decision unit 3 is the my input of the gated switch 10, and the information output is the output of element And 17. The first and second control inputs of the gated comparator 10 are the second 1/2 and sixth Ui-lin control-inputs of the decision unit 3. The control inputs of the first

11, the second 12 and third 13 switches are the third UZ, the fourth L / 4 and the first Ui control inputs of the decision block 3, respectively. The second input of the AND element 17 is the fifth control input Us, and the information input of the switch 13 is the seventh control E input of the decision unit 3. The output of the gated comparator 10 is connected to the information inputs of the switches 11 and

12, the outputs of which are connected respectively to the inputs of the memory elements 14 and 15. The outputs of the memory elements 14 and 15 are connected to the inputs of the adder 16 modulo two, the output of which is connected to the first input of the element 17. The information output of the switch 13 is connected to the input of the memory element 15.

A trigger read amplifier can be used as a gated comparator 10. However, the known amplifier triggers on the falling edge of the control signal - U2, the signal of the control unit 5. In order to ensure the triggering on the leading edge in this implementation, the signal U2 can be fed through an inverter to the first control input of the gated comparator 10. The second control input of the gated climber 10 is reverse

trigger trigger input. As a result, the state diagram of the gated comparator 10 is as follows | 0, U2 0;

U out 0.1) 2 1 when U in U U clay: 1.U2 1 when U in Uglin

where UBX, UBUX are the values of the input signals

0 and the output of the gated comparator 10,

As switches 11-13, keys based on MOS transistors can be used. Input cells can be used as memory elements.

5 adder 16 modulo two, as used in dynamic logic elements. In this case, modulator two adder 16 is fabricated based on MOS technology.

0 Control unit 5 (FIG. 4) contains two

counting trigger 18 and 19, the generator 20 pulses, the binary counter 21, the delay element 22, the element And 23, the element And 24 with inverse input. The start input of the REC unit 5 of control is connected to the setup input S of the counting trigger 18, to the reset inputs R of the binary counter 21 and the counting trigger 19 and to the first output Ui. The second output IJ2 of control unit 5 is connected to

0 direct output of the generator 20 pulses, the installation input S of the counting trigger 19, the counting input C of the binary counter 21 and to the input of the delay element 22, the third output UZ - to the output of the element 23, the fourth

5 output LM - to the output of the element I with an inverted input, fifth output Us - to the inverted output of the generator 20 pulses, the sixth output Ue - to the output of the counting trigger 19. The output of the counting trigger 18 is connected to

0 E1 start signal generator 20 pulses. The overflow output P of binary counter 21 is connected to the synchronization inputs C of the counting triggers 18 and 19. The first output of the first trigger of the binary counter

5 21 is connected to the second input of the element And 23 and to the inverse input of the element And 24 with the inverse input. The output of the delay element 22 is connected to the first input of the AND 23 element and to the forward input of the AND 24 s element

0 inverse input.

The generator 20 pulses can be performed according to a known scheme. The delay element 22 can be any one that provides a delay of the signal for the switching time5 of the first trigger of the binary counter 21. If it is necessary to program the control unit 5, a pulse generator 20 with variable pulse duration and a binary counter 21 s can be used to obtain different intensity levels conversion factor. So, for example, in the present implementation, various RC circuits of the pulse generator 20 can be switched, and as a binary counter 21 in this case, a counter with a variable division factor can be used.

The device works as follows.

The operation of the device in extracting such signs of images as areas of different intensities is based on transforming the input analog image into a proportional intensity electric signal in each photodetector element 1, comparing the value of this electric signal with the linearly varying time signal from the output of the generator 4 in crucial blocks 3 and recording the coincidence time of these two electrical signals, which is proportional to the intensity of the image element corresponding to the given cell. Since the device operates cyclically, and the cycle consists of N different cycles, the coincidence time is determined to the accuracy of the cycle. The time diagram shows the levels of optical streams F1 and F2 incident on the optical inputs of the photodetector elements 1, which correspond to the eighth and fourth levels of intensity. With the increasing nature of the change in the electrical signal at the output of the generator 4 in the first cycle of the work cycle, areas with the lowest intensity are selected, and in the Nth cycle with the maximum intensity. In this case, the range of intensity values included in one level is determined by the pulse following period of the pulse generator 20 included in the control unit 5, and the number of levels is determined by the number of pulses in the cycle (in the considered example), i.e. the conversion factor of the binary counter 21 of the control block 5. The content of the binary counter 21 thus clearly corresponds to the number of the intensity level to be selected.

Each device operation cycle consists of two parts: reading information from the output of the gated comparator 10 through the second U2, third Kz and fourth U "signal of the control unit 5 and processing the read result with outputting the result in optical form from the optical output of the corresponding electro-optical converters 2 displays during the pulse at the fifth output Us of the control unit 5. Every odd clock read signal from gated outputs

the comparators 10 are produced into the first memory elements 14 through the first switches 11 opened by the third signal Oz of the control unit 5, and even even cycles into 5 second memory elements 15 through the fourth LM signal opened by the control unit 5, the second switches 12

The criterion for the operation of the corresponding electro-optical converters of the display unit 2 in the i-th cycle is the presence of a combination of logical O and logical 1 or logical 1 and logical 0 at the outputs of the memory elements 14 and 15. This corresponds to case 5 when, in the i-th cycle, in the corresponding cells of the equal-intensity region, the signal levels at the information input and at the second control input of the gated comparators coincide.

0 10. Then, at the outputs of the corresponding adders 16 modulo two, a logical 1 signal appears, which passes in the second part of the i-th cycle through the elements 17 And opened by the signal at the fifth control input of the decisive blocks 3 and causes the operation of electro-optical converters block 2 display.

The combination of two logical 1 at the output of memory elements 14 and 15 means that

0 the coincidence of the levels of electrical signals in the previous cycle does not occur, and two logical O - that the coincidence and the selection of the corresponding areas occurs in earlier cycles.

5 The cycle of the device starts with

trigger signal sent from an external device, such as a remote control. By this signal, the counting trigger 18 is set to one state, zeroed 0 with the counting trigger 19 and the binary counter 21. In addition, this signal, passing through the first control Ui input to the decision blocks 3, switches the third switches 13, which causes the logical 1 in

5 second memory elements 16 from voltage source 6.

A logical signal 1 from the output of the counting trigger 18 initiates the generator of 20 pulses. Start of the first

0 pulse from the direct output of the pulse generator 20 sets the counting trigger 19 to the state of logical 1. The output signal from the counting trigger 19 passes through the sixth output Uo of the control unit 5 to

5 input synchronization generator 4 and starts it. The generator 4 begins to generate a linearly varying voltage until the end of this cycle of operation of the device. Consider the first hack of the device.

The first pulse, acting through the second control input U2 of the decision blocks 3 to the first control input of the gated comparators 10, reads information from the photo-receiving elements 1. According to the operation diagram of the gated comparator 10, its output will be a logical O signal, if the signal level on the information the input is lower than the signal level Uglin on the second control input of the comparator, otherwise the signal will be logical 1,

The third Uz and fourth 1) 4 signals of the control unit 5 provide alternate switching of the first 11 and second 12 switches. This is achieved by the elements AND 23 and 24 of the control unit 5. Each odd pulse defined by a single state of the first trigger of binary counter 21 opens element AND 23 and a pulse from the direct output of generator 20 pulses passes through delay element 22 and element 23 to third output OU of control unit 5. Each even pulse determined by the zero ratio of the first trigger of the binary counter 21 opens an AND 24 element with an inverse input and the pulse passes to the fourth output 1M of the control unit 5. Consequently, the first pulse, being odd, causes the switching of the first switches 11 and the recording of the signal with the output of the gated comparators 10 into the first memory elements 14.

In the second part of the first cycle, a pulse is generated from the inverted output of the pulse generator 20, which is fed to the fifth control inputs Us of the decision blocks 3. This pulse opens AND 17 elements. Modulators 16 modulo two perform summation containing the first 14 and second 15 memory elements. ti. If logical 1 is written in both memory elements, which means that the signal level at the second control input is gated by the signal at the information input, the output of the corresponding totalizers-16 modulo two will be logical O, and the corresponding electro-optical converters of the display unit 2 will not work. If in the first memory element 14 the logical O is recorded, which means in the first cycle the equality of zero, incident on the corresponding cells of the optical flow, the first level of brightness, then the signal of logical 1 at the output of adders 16 modulo two, passed through the open elements And 17 , will trigger the corresponding electro-optical converters of the display unit 2.

During the first part of the next second bar (and then every even

tact) the second memory element 15 is overwritten through the open switch 12. Similarly, the contents of the first 14 and second 15 memory elements are analyzed during the second part of the cycle

0 and in the case of a combination of logical O - logical 1 or logical 1 - logical O will be; the corresponding electro-optical converters of the display unit 2 are activated.

5 During subsequent cycles, areas with higher intensities are selected. The last Nth pulse from the direct output of the pulse generator 20 overflows the double counter 21, passes its overflow output P and drops the counting triggers 18 and 19 at the back front. The logic signal O at the output of the counting trigger 18 stops the pulse generator 20, and on

5 output of the counting trigger 19 - generator 4.

Claims (2)

Claims. 1, A device for extracting features of images containing photodetector elements, the optical inputs of which comprise information inputs of the device, decision units, outputs of which are connected to the inputs of a display unit, a control unit, the first output of which is connected to the first switching inputs of decision units, that, in order to improve the accuracy of the device, it contains a linear voltage generator, a reference voltage source and a gain unit, the second, third, fourth and fifth outputs of the unit Regents connected respectively to the first gate inputs of the second switching input, the third switching inputs and inputs the survey decisive 5 blocks, the second gating inputs of which are connected to the generator output of a linearly non-variable voltage, the reference input of each decision block is connected to the output of the reference source 0 voltage, the information inputs of the decision blocks are connected to the outputs of the respective amplification blocks, the inputs of which are connected to the outputs of the photodetector elements. The sixth output of the control unit is connected to the synchronization input of the generator of linearly varying voltage. 2. The device according to claim 1, characterized in that the decision block contains a gated comparator, three switches, two memory module, modulo-two adder, and AND element, the information and control inputs of the first switch are respectively the reference and first switching inputs of the block, the forward input of the gated komparator is the information input of the block, the first and second gates of which are the control inputs of the gated comparator, the output of which is connected to the information inputs The ladders of the second and third switches, the control inputs of which are the second and third switching inputs of the block, respectively, and the outputs are connected to the inputs of the corresponding memory elements, the outputs of which are connected to the input of the modulo two, the output of which is connected to one input of the And element, the other the input of which is the polling input of the block, and the output of the AND element is the output of the block. / BUT  V ъ / х  L L A L % Utg Un Un UTS iG6 5 1  //// 7 ///////////////// ////////// 7 7 ////// l M 77 AND I / 72 GZ G5 7 talws "4J FLP P P P P P P P P G 1G 1GPGG 1GPG 1P P P P P P 5