SU1656557A1 - Device to check parameters - Google Patents

Abstract

The invention relates to instrumentation engineering and can be used to create technical means for controlling complex objects. The purpose of the invention is to increase the speed of the device. The device contains a program setting unit 1, a comparison unit 2, a control unit 3, a result output unit 4, a parameter analyzer 5 and a switch 6. The device provides two-step parameter control, and the repeat control is used only when necessary, thereby increasing the speed of the device, as well as the reliability of the control. 2 h p f-ly. 10 il.

Description

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Claims (3)

Claim 1. A device for monitoring parameters, comprising a switch, a parameter analyzer, a result output unit, a program controller and a control unit, information inputs of the switch are connected to the inputs of the device for connecting to the outputs of the monitoring object, control inputs are connected to the first group of information outputs of the program setter, and the output - with the information input of the parameter analyzer, the first, second and third groups of information inputs of which are connected respectively with the second, third and fourth groups of information outputs the program sensor, the first and second control inputs of the parameter analyzer are connected respectively to the first and second control outputs of the program master, the first and second information outputs and the group of information outputs of the parameter analyzer are connected respectively to the first and second information inputs and to the group of information inputs of the result output block, the first the control input of which is connected to the first output of the control unit, and the second control input to the second control output of the program setter, unitary enterprise ulation analyzer output parameters associated with a first input of the control unit, the second output of which is connected to the first control input of the set point programs, second and third control inputs are connected to inputs start and reset the device, respectively, wherein. that, in order to improve performance, a block has been introduced into the device In comparison, the first group of information inputs of which is connected to the group of information outputs of the parameter analyzer, the second group of information inputs of the comparison flea is connected to the fifth 5 group of information outputs of the program setter, the fourth control input of which is connected to the first output of the comparison unit, the second output of which is connected to the second input control unit. 10, the third output of which is connected with the fifth control input of the program setter, the third input of the control unit is connected to the third control output of the program setter. fifteen 2. The device according to claim 1, the clause being that the control unit comprises a delay element, first and second AND elements, a trigger and a pulse shaper, an input of the delay element and a first input of the first 20 AND elements are the first and second inputs of the block, respectively, the output of the delay element is connected to the second input of the first element And and the first input of the second element And is the second output of the block 25, the output of the pulse shaper serves as the third output of the block, the input of the pulse shaper is connected to the direct output of the trigger, exit second AND gate is the first output of the inverse output of the flip-flop 30 is connected to the second input of the second AND gate, counting trigger input connected to the output of the first AND gate and the reset input of the flip-flop is the third input block. 3. The device according to claim 1, characterized in that the program controller comprises a control unit, a block of RAM registers, a permanent memory block, an address counter, an address register, two groups of amplifiers and two amplifiers, the first, second 40 and third the inputs of the control node are the first, second and third control inputs of the program setter, the address input of the read-only memory node is connected to the information output of the address counter 45 sa, the group of high-order bits of the installation inputs of the address counter is connected to the first group of information outputs b flash memory registers, the group average discharge setting input address counter - a group of information outputs of the address register group LSBs setting input address counter - a group of input digital zero, and the count input - a first exit ₂ home node control, the second output of which is connected with the input of the address counter setting, and the third output of the control node through the first amplifier is connected to the first reset input of the RAM register block, with the address counter reset input, the address reset input and it also serves as the second control output of the program setter, the third control output of which is the fourth output of the control unit, also connected to the second reset input of the RAM register block, the information and address outputs of the permanent memory block are connected through the first and second group of amplifiers with information and address inputs block of RAM registers, the first control output of the block of RAM registers is connected to the control input of the control node, the fifth output of which is through the second an amplifier connected to the input license to renew entry block RAM registers and the read enable input blo ka permanent memory directly, the second, third, fourth, fifth and sixth group of information outputs of memory registers are the first block. the second, third, fourth and fifth groups of information outputs of the program master, the first control output of which is the second control output of the block of the memory registers, and the fourth and fifth control inputs of the program master are the information input and the input of the address register permission. Figure 1 Fig.Z Fig. 4 (~ Start \ I \ Reset („czr :) U ---------..... G Start (7p1 ”T WE enter in bl. 6.5 (8.9) and 2 initial data (switching, range, KN, K8, codes, zones) --No start ADC \ Perform in block 5 conversion 8 code and analysis of the parameter Generate and issue “Г” “Р _г> 3Ηακ-βδηοκΝ4,“ КА ”-8 block 5,“ X ”and” Sign to block ?. 1st ^e No at The prototype. assessment ι trust zone Form in bl.Z and give in bl A A “SI '' (delivery of the district), and in block 1 the signal'- P2 (dalmie) 7 Go to control the next pair of met- C End) Form 6 bl.s. 3 and give signals in bl. 1 »L? and "MA" MM »N .. (generate vdl.2 and issue in dl.1 control signals about the zone of the actual location of the control result ---------------------—...... Ψ .. ............ -................... Change 8 acc. with ave. signal. from 8l. 2 initial data (range, Kn, Cd) in block 5 (dlZid) ---------------- Г 7 '-------------- Output from bl.1 blbl.5 (bl.8) signal “Start A Tsy: ςξξ ........:, 1 ——— Figure 5 C7 Second ^ Conversion first ^ '' <$ pureen ^ first “ ____ * _ enter b _x and perform a comparison of $ x with a confidence zone • W Generate and Issue a signal to enter the contents of the result register ^ ® into the output block ______ w ________ Generate a signal to change the range of the ADC („MA ^p ) Fig! FIG. 8 ^and H \ and _H + fan g L - Z / '! ¹ - {-------, ----------- 1 ----------------------- I ί. ~ | ί _ _HO Nal m _{and H f} to the parameter I | 27 Ufarr permissible deviation of the parameter [ί ² βχ-Value of the relative —-ί 'parameter deviation M _1f Μη - control points. FIG. 9 ROM word address format Senior bit. ^ ROAcm * We are modernizing S RCAmip part of the word We increase in the course of the program in the Hundred part of the word ... thousands, hundreds dozens units FIG. 10