SU1656539A1 - Majority signal selection device - Google Patents

Abstract

The invention relates to automation and computing technology and can be used in the construction of redundant control systems of increased accuracy, in particular in systems for processing and transmitting service and measurement information. The goal is to improve the accuracy of the device. The goal is achieved by introducing into the device the first 1, second 2, third 3 and fourth

Description

The invention relates to automation and computing and can be used in the construction of redundant automatic control systems of increased accuracy, in particular in systems for processing and transmitting service and measurement information.

The aim of the invention is to improve the accuracy of the device.

The invention consists in increasing the reliability and accuracy of the device operation by separately processing the higher code message bits, which include the encoded service message and the high bits of the measurement information, and the lower bits of the code messages, which in one measurement cycle can differ in channels counting different values of random errors.

The drawing shows a functional diagram of the device.

The device contains the first 1, second 2, third 3 and fourth 4 shift registers to the right, the first 5 and second 6 storage registers, the majority element 7, the average value calculation unit 8, the decoder 9, the switch 10, the multiplexer 11, the first 12 and the second 13 counters , first 14, second 15, third 16 and fourth 17 triggers, first 18, second 19, third 20 and fourth 21 modulo two, first 22, second 23 and third 24 blocks of elements And, first 25, second 26, third 27 , the fourth 28, the fifth 29 and the sixth 30 elements OR, the first 31, the second 32, the third 33, the fourth 34 elements AND, 35 ent delay odnovib- Rhatore 36, the block elements 37 or the first 38 - 40 data inputs of the third device 41 inputs timing gate device 42 outputs 43 an error signal. 44 clock and 45 information, and the output 46 readiness of the device.

The 1–3 shift registers are designed to receive, store and output the lower bits of the measuring parts of the input sequences, each of which

contains P bits. Recording information in registers 1 - 3 is carried out in P cycles on the falling edge of the clock pulses, coming from the output of the element 32. The reset of registers to the O is done after the end

processing the message in the device and recording the average value of the measured parameter to the register 5 by storing the signal from the single output of the trigger 15.

Shift register 4 is intended for receiving, storing and issuing majorized bits of the service part and higher bits of the measuring part of the input sequences (C bits).

Information is written to register 4 in C clock sync pulses coming from the output of element 32. When writing the fluctuating part of the parameter being measured (P clock) information is not recorded in register 4, since it is blocked by element 31, but the shift of the recorded information continues until the entire message is received. The bit width of register 4 must be equal to the maximum number of bits of the message code.

The reset of register 4 in O is performed in the same way as registers 1-3

Register 5 is designed to receive, store and output the generated output sequence, as well as to store and output to the device output 43 an error signal about the distortion of the output sequence.

Register 6 is designed to receive, store and issue codes of the length of the entire input sequence and its first part C. These codes are located in the higher bits of the message and occupy K bits.

Record in register 6 of these codes occurs at the K lower information outputs of register 4 after they are received by the falling edge of the pulse arriving at the synchronous input of register 6 from output 12.1 of counter 12.

The majority element 7 forms the service part and the most significant bits of the measuring part of the output sequence by granularizing the service parts of the input sequences.

The average calculation unit 8 determines the arithmetic average of the fluctuating part of the parameters recorded in registers 1–3 and satisfying the parity criterion. The average value of the parameter is applied to the outputs of the 8.1 block. Output 8.2 of the block receives the value of the sum of the parameters, which will be equal to the value of the parameter if an error is detected in the two channels.

The decoder 9 converts the signals. formed by modulo-two adders 18–20 and indicative of the distortion of the information parts of the input sequences, and outputs signals that control the process of their processing. The signal at output 9.0 indicates the absence of distortion, the signals at the outputs 9.1, 9.2 or 9.4 - the distortion of one of the three sequences, the signals at the outputs 9.3, 9.5 or 9.6 - the distortion of one of the three sequences, the signal at the output 9.7 - distortion of all three information parts of the input sequences.

The switch 10 switches to the information input of the register 5 the result of processing the information parts of the three input sequences. When the signal at its control input is zero, the output from the output 8.1 of block 8, which corresponds to the average value of the undistorted sequences, and at one at the control input, the output from output 8.2 of the block 8, which coincides with the code of the only undistorted input sequence .

Multiplexer 11 converts a parallel code from the output of register 5 into a serial one. The output signal appears only in the presence of a sync pulse. A code from the output of the counter 13 is fed to the address input of the multiplexer 11, by which the bits of the first part of the output sequence and then the second part of it are sequentially selected. Counter 12 counts the code length of the values of the C and C + P values of this sequence, as well as the length of the first bits) part and the total length (Cf4 P bits) of the input sequence, producing pulses at the outputs 12.1. 12.3 and 12.2 respectively.

Counter 13 generates address codes

at the input of the multiplexer 11. It starts to operate when a single signal appears at its control input when the processed message is rewritten to

register 5. A change in the state of the counter occurs on the falling edge of the clock pulse, which arrives at its counting input from the input 41 of the device. Before starting the counting of addresses on the trailing edge of the pulse,

incoming from the output of the element 33 to the synchronous input of the counter 13, the number of free bits in the register 5 is written to it from the inverse information outputs of the counter 12. Therefore, the multiplexer addresses 11

begin to form from the number of the first occupied bit in register 5.

The trigger 14 forms a time window during which the full input sequence is received and registers 1-4. It is set to a single value by a signal from the device input 42 and serving as the gate of the beginning of the input sequence. This signal is generated by the source of the message.

The flip-flop 14 in O is reset by a pulse from the output 12.2 of the counter 12, which is issued after the last bit of the message has been received by the device.

The trigger 15 is a device readiness trigger for receiving the next message. It is set to the one state by the falling edge of the pulse from the output of the AND 33 element, which is generated upon completion of the processing of the previous message in the device and after writing it to register 5.

The trigger 16 generates signals that control reception of the first (one at the inverse output) and the second (one at the forward

output) parts of the input sequences. The trigger 17 forms a time window. during which the processed message is issued from register 5 through multiplexer 11 to the output 45 of the device. The trigger 17 is set to a single value by the falling edge of a single signal from the output of the AND 33 element, which occurs after the reception of the input sequence in registers 1-4 is completed. Reset

the trigger 17 in O is carried out by a single signal from the output of the one-shot 36, when the counter 13 is folded.

Modulo two adders 18–20 control parity of incoming 38–40 lower bits on inputs

measuring parts of the input sequence after writing them to registers 1 - 3, respectively. With an odd number of units in this part of the sequence, a single signal is generated at the output of element 18 (19, 20).

Modulo two adder 21 controls the parity of the majoritarianized sequence of service and higher bits of the measuring part of the input code messages. With an odd number of units in this part of the message, a single signal is generated from the output of element 21.

The blocks of elements 22-224 permit the arrival at the information inputs of block 8 of the information parts of the input sequences, if the parity check did not detect their distortion. For this, a signal from the outputs of elements 18-20, respectively, is supplied to their inverted inputs.

The OR 25 element generates a signal about the distortion of one of the three, and the OR 26 element generates two of the three received in the registers 1 - 3 information parts of the input sequences.

The OR element 27 generates a common error signal, first, when parity checks are detected in the majorized part of the message, and, second, when all three information parts of the input sequences received in registers 1 to 3 are distorted.

The OR element 28 transmits a single signal at the end of the first part of the message and at the end of the second part of the message, which is used when switching the trigger 16.

The OR elements 29 and 30 form signals of a non-zero value of the counter 13 and register 5, respectively.

Element And 31 serves to transfer to the information input of register 4 only the service and non-fluctuating measuring part of the input message. After the reception of these parts of the message has been completed, it is closed on the inverted input of single signals from the output of the trigger 16.

Element And 32 forms a sequence of pulses, the number of which is equal to the number of bits in the received message.

Element And 33 serves to generate a pulse signal of the device readiness for issuing the next message, as evidenced by a single signal from the inverse output of the trigger 14, indicating that the reception of the next message ends, and a single signal from the inverse output

trigger 17, indicating the end of the previous message. In the presence of these signals through the element And 33 passes shifted clock pulse from the element 35 of the delay.

Element And 34 provides for the transmission of shifted sync pulses from the output of delay element 35 to the control input of multiplexer 11 only when

0 register 5 is recorded non-zero information and the trigger 17 is in a single state, i.e. counter 13 is working.

Delay element 35 serves to obtain a clock-shifted sequence of clock pulses. The time delay of the clock pulses must be greater than the time of the sequential operation of the element 32 of the counter 12, trigger 14, and the element 33.

The block of 37 elements OR is used to correctly place in the register bits 5 lower bits of the message from the output of block 8.

The one-shot 36 generates a pulse

5 indicating the completion of the issuance of the next message from the device. It is triggered by the falling edge of the signal from the output of the element OR 29.

The device works as follows.

0In the initial state registers 1-4,

register 6, counters 12 and 13, triggers 14, 16 - 19 are set to the zero state, and the trigger 15 is set to one (setting circuit to the initial state is not shown in the drawing).

5 Before the beginning of the arrival of information at the inputs 38–40 of the device in the period between the sync pulses, the gate 42 arrives at the entrance 42, which announces the beginning of the transmission of information. In this case, the trigger 14 is switched to the single state and opens the element E 32, through which the clock pulses from the input 41 of the device begin to arrive at the synchronous inputs of registers 1 to 4 and to the counting input of the counter 12. At the same time, the information inputs of the registers 1 to 3 are closed with a zero signal trigger 16, and the element And 31 the same signal is open. On the falling edge of each sync pulse of the next major majorized bit

The 0 message containing the service part and the non-fluctuating measuring part of the message is written to register 4. And the previously recorded higher bits are shifted in register 4 to the right. AT

5 at the same time, the contents of counter 12, which counts the number of bits received, is incremented by one.

When to register 4 will be accepted all K senior bits of the message containing information about the length of the entire message C + P

and its first part C, at the moment of action of the sync pulse shifted by the delay element 35 at the input of the counter 12 at its output 12.1, a pulse is generated. With its falling edge, this impulse will write to the register b codes of the values of the values C and C + P.

When the value of counter 12 becomes equal to the length of the first part of the message, at its output 12.3, the arrival of a synchronized pulse shifted by the delay element 35 results in a single pulse, which, having passed through the OR element 28, switches the trigger 16 to the unit state. The signal from the single output of the trigger 16 will close the element And 31 and open the registers 1 to 3 to receive information from the inputs 38-40 of the device. From this point on, the second part of the message from the three channels will be recorded in registers 1–3, and in register 4, the recorded information will continue to shift to the right with a record of bits of zeros freeing to the left.

When the contents of counter 12 become equal to the value of C + R, which means that the entire message has been received into the device, at its output 12.2 a shifted clock pulse triggers a pulse that will reset trigger 14 to the zero state, thereby closing element I 32 and prohibiting the recording of information into input registers 1 - 4. The same impulse of counter 12, having passed through the element OR 28, will transfer the trigger 16 to the zero state.

In this case, the element AND 33 is opened and transmits a sync pulse delayed by the delay element 35. By this pulse, the inverse value of the counter 12 is written to the counter 13, and the triggers 15 and 17 are set to one. The device is put into information mode. At the same time, a single signal appears at the output 46 of the device, indicating that it is ready to receive the next message.

Before the start of issuing a message, the impulse from the output of the AND 33 element with its back edge will write the processed message to the register 5. At the same time, the processing of the message, except for majorization at the input of its older part, will be as follows.

The parallel codes of the fluctuating part of the measurement information, corresponding to the three measurement channels, arrive at the modulo-two adders 18–20, respectively. If a parity violation is detected in one of the channels, then the corresponding modulo two adder will generate a single signal, which will be sent to the inverse control input of the corresponding AND element block (22-24). This block of elements And will prohibit the transfer of the failed part of the message to. average calculation unit 8. At the same time, the signals from the outputs of the modulo-two adversts 18-20 are fed to the inputs of the decoder 9, which, together with the OR 25-27 elements, provides an analysis of the result of checking the evenness of the fluctuating part of the measurement. If in all three

0 error channels were not detected, then all three messages go to the inputs of the average calculation unit 8, which determines the average value from three measurements, and through the switch 10 transmits to the inputs of the block

5 37 elements OR. If a failure is detected in one channel, the OR 25 element generates a single signal, which is fed to the control input of block 8, and the latter calculates the average value of

0 to two measurements. If the failed messages are detected in two channels at once, a single signal appears at the output of the OR 26 element, the second information input of the switch 10 opens, and the first 5 closes, and the measurement information from the single channel without failures comes from the output 8.2 block 8 through the switch 10 to the inputs of the block 37 elements OR. If errors are found in all three

0 channels or if an odd even error is detected in the first part of the message by modulator 21 modulo two, then a single signal is received at the output of the element OR 27 will be recorded in a special zero 5 register error error 5 and will be output at the output 43 of the device error. The corresponding bit inputs of the block 37 elements OR receive signals from the output of the switch 10 and the signals of the lower bit 0 to the information outputs of the register 4. As a result, the output of the register 5 in the general case will contain all the bits of the second part of the message and the lower bits of the first part posts. In this case, the smallest bit of the variable of the first part of the message will be connected with the most significant bit of the second part. Register 5 records the most significant bits of the first part of the message.

0Single trigger output 15

will reset registers 1-4 and counter 12 in О, preparing them to receive the next message. In the counter 13, after recording the inverse value of the counter 12 in it, the code of the bit number of the register 5 will be written, followed by the most significant bit of the message. With a single signal from the direct output of the trigger 17 to the control input of the counter 13, counting of the input clock pulses will begin. The counter value 13, which determines the number of the next bit of the message in register 5 to be outputted at the device output 45, goes to the address inputs of the multiplexer 11. At a non-zero register 5, the output signal of the OR 30 element is a single signal that opens AND 34, and through it, the shifted sync pulses arrive at the control input of multiplexer 11, permitting the issuance of the next message bit only when a new value of counter 13 is set. Pulses from the output of element 35 also arrive at stroke device 44, determines the boundaries of cycles of the output sequence.

When the delivery of the entire message is completed, the counter 13 will assume a zero value, Element OR 29 will generate a zero value at its output and a single vibrator 40 will operate, the pulse of which will set the trigger 17 to the zero state. A zero signal from the direct output of the trigger 17 will prohibit the operation of the counter 13, and a single signal from its inverse output will open the element AND 33, preparing it for the launch of the next operation of issuing information.

Claims (1)

If by the time the next message is completed, the next message has already been completely received in registers 1-4 of the device, then the AND 33 element will be opened with single signals from the inverse outputs of the flip-flops 14 and 17 and the shifted sync pulse will start the next message operation through the AND 33 element. If by the time the next message is completed, the reception of the new message is not yet completed, then the AND element 33 is closed with the zero signal from the trigger 14, and the issue operation is postponed until the moment of the reception is completed. An invention of a device for the majority choice of signals, containing the majority element, the first trigger, the first and second elements AND, the first and second elements OR, characterized in that, in order to improve accuracy, the first, second, third and fourth right shift registers are entered into it , first and second storage registers, average calculation unit, decoder, switch, multiplexer, first and second counters, second, third and fourth triggers, first, second, third and fourth modulo two, first, second and third Loka elements And, third, fourth, fifth and sixth OR elements. the third and fourth elements And, a block of elements OR, a delay element and a one-shot, the first, second and the third information inputs of the device are connected to the information inputs of the first, second and third shift registers to the right and to the corresponding inputs the majority element, the output of which is connected to the first input of the first element I, the output of which is connected to the information input of the fourth shift register to the right, information outputs of the first, 0 of the second and third shift registers to the right are connected to the information inputs of the first, second and third blocks of the And elements, respectively, and to the corresponding inputs of the first, second, and 5 of the third modulo-two adders whose outputs are connected to the corresponding inputs of the decoder and to the inverse inputs of the first, second and third blocks of AND elements, the information outputs of which are connected to the corresponding information inputs of the average calculation block, the first and second outputs of the sum and average value connected to the first and second information inputs of the switch, respectively; the first, second and fourth outputs of the decoder are connected to the corresponding inputs of the first IL element And the output of which is connected to the control 0 to the input of the average calculation unit, the third, fifth and sixth outputs of the decoder are connected to the inputs of the second OR element, whose output is the control input of the switch, the seventh output of the decoder is connected to the first input of the third OR element, the information outputs of the switch are connected to the first group of inputs block of elements OR, information outputs of the fourth shift register 0 to the right are connected to the inputs of the fourth modulo-two adder and to the first information inputs of the first storage register, the first and second groups of lower bits of the information outputs of the fourth right shift register are connected respectively to the information inputs of the second storage register and to the second group of inputs of the block of OR elements, the outputs of which are connected to the second information inputs of the first storage register, the output of the fourth modulo two is connected to the second input of the third OR element, the output of which By connecting the input of discharge errors of the first register 5 of the storage, the output of which is the output of the device error signal, the gate input of the device is connected to the single installation input of the first trigger and to the installation input to the second trigger, the single output of which is connected to the inputs resetting the first to fourth shift registers to the right and the first counter and is the device ready output, the direct output of the first trigger is connected to the first input of the second element, the second output of which is the device synchronization input, and the output is connected to the synchronous inputs of all four shift registers to the right and to the counting input of the first counter, the information outputs of the second storage register are connected to the information inputs of the first counter, the first output of which is connected to the synchronous input of the second storage register, and The second output is connected to the installation input of the first trigger and to the first input of the fourth OR element, the second input of which is connected to the third output of the first counter, and the output connected to the counting input of the third trigger, whose direct output is connected to the control inputs of the first three shift registers to the right and to the second input of the first element I, the inverse information outputs of the first counter are connected to the information inputs of the second counter, the information outputs of which are connected to the address inputs of the multiplexer and to the inputs of the fifth OR element, the output of which is connected via the one-shot to the reset input of the fourth trigger, the direct output of which is connected to the control input of the second counter, to the third input of the fourth element I. The synchronous input of the device is connected to the counting input of the second counter and through the delay element - to the enable input of the first counter, and to the first inputs of the third and fourth elements And, the second and third inputs of the third element And are connected to the inverse outputs of the first and fourth triggers, respectively, the output of the third element I is connected to the synchronous inputs of the first register of storage and the second counter, as well as to the synchronous inputs and single installation inputs of the second and fourth triggers, the information output of the first storage register is connected to the information inputs of the multiplexer and the inputs of the sixth element OR, the output of which is connected to the second input of the fourth element And, the output of which is connected to the control input of the multiplexer and is the clock output of the device, and the output of the multiplexer is the information output of the device ..