SU1644371A2 - Digital pulse-width modulator - Google Patents

Description

one

(61) 1478316

(21) 4687801/21

(22) 28004089

(46) 04/23/91. Bup. Number 15

(71) Kuibyshev Polytechnic Institute. V.V. Kuibyshev

(72) OSS. Galitskov, S.N. Lysov, A “V about Starikov, A.G0 Makarov

and AOU Tikhonov

(53) 621,376.54 (088.8)

(56) USSR Copyright Certificate 1 1478316, cl. H 03 K 7/08, 1987,

(54) DIGITAL WIDE AND PULSE MODULATOR

(57) The invention relates to a pulse technique and can be used in information transmission and conversion devices, as well as key power amplifiers. The purpose of the invention is to increase reliability

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The modulator contains counters 1, 2 pulses, counting triggers 3-5, trigger 6 characters, generator 7 rectangular pulses, elements 8-11, matches, drivers 12, 13 pulses, inverter 14, elements 15-17, switches 18, 19 , restriction unit 20, resetting node 21 and buses: output 26, 27, input signal 28, sign 29. The introduction of the IS-HE element 22 into it, the match elements 23, 24, and trigger 25 eliminates the simultaneous appearance of high-level signals on both output tires, thereby expanding its scope by using a modulator in those devices where the simultaneous occurrence of high-level signals on both output buses can lead to a crash. tuition. 2 yl

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The invention relates to a pulse technique, can be used in devices for transmitting and converting information, as well as in key forces of power bodies, and is an improvement of the invention according to the author. ev about F 1478316.

The aim of the invention is to increase reliability by eliminating the simultaneous appearance of signals at both outputs of the device.

FIG. 1 shows a functional diagram of a digital pulse width modulator; fig 2 is a limit block.

Digital pulse-width modulator contains counters 1 and 2 pulses, counting triggers 3-5, trigger 6 NAC, generator 7 rectangular pulses, elements 8-11 matches, drivers 12 and 13 pulses, inverter 14, elements OR 15- 17, switches 18 and 19, limitation block 20, reset node 21, NAND element 22, coincidence elements 23 and 24, trigger 25, output buses 26 and 27, input bus 28, symbol bus 29, with generator output 7 rectangular pulses connected to the counting input of the counting trigger 3 and the first inputs of the elements OR 15 and 16, the second inputs of the cat The outputs are connected respectively to the direct and inverse outputs of the trigger 6 characters, and the outputs respectively to the direct and reverse counts of the pulse counter 1, the transfer outputs of which are connected to the inputs of the coincidence element 8, the output of which is connected to the first input of the OR element 17 the output of which is connected to the input of the Pulser 12 and the first input of the coincidence element 9, the second input of which is connected to the output of the pulse former, and the output to the counting input of the counting trigger 4, the direct output of which is connected to the second input ohm of the element OR 17, and the inverse output to the first input of the switch 18 and the second input of the switch 19, the control inputs of which are connected to the forward output of the 6-character trigger, the second input of the switch 18 and the first input of the switch 19 to the forward output of the trigger 5, and the outputs - with the inputs of the element AND-NOT 22 and the second inputs of the elements 23 and 24 matches, the outputs of which are connected respectively to

output buses 26 and 27, and the first input - with the inverse output of the trigger 25, the installation input in 1 of which is connected to the output of the NANDEM element 22, and the installation input to O - with the output of the reset node 21, the second input of the coincidence element 11, the installation input in About the counting trigger 4 and the installation input in About the counting trigger 5, the counting input of which is connected to the output of the coincidence element 10, the second input of which is connected to the output of the Shaper 12 pulses and the first input to the input of the shaper 13 pulses, the first input of the coincidence element 11 and the output counter 2 pulse The counters, the bit inputs of which are connected to the common bus, the counting input is connected to the output of the counting trigger 3, and the information recording input is connected to the output of the coincidence element 11, the information entry input of the pulse counter 1 and the input of the inverter 14, the output of which is connected to the first trigger input 6 a sign, the second input of which is connected to the character bus 29 and the sign input of the limiting unit 20, the bit inputs of which are connected to the input signal buses 28, and the outputs to the bit inputs of the pulse counter 1.

The device can be implemented, for example, on integrated circuits of the K155 series, namely: counters 1 and 2 on K155, IE7, triggers 3-6 and 25 on K 155TM2, coincidence elements 8-11, 23 and 24 on K 155L1 , shapers 12 and 13 pulses - on K 155AG1, inverter 14 - on K 155LN1, elements OR 15 - 17 - on K 155LL1, switches, 18 and 19 - on K 155KP2, generator 7 of rectangular pulses - on K 155L with quartz stabilizer or with the time reference driver in the feedback circuit between the inverters.

The limitation unit 20 (FIG. 2) contains, for example, a group of 30 elements OR, a group of 31 elements of coincidence, an element AND-NO 32, elements OR 33 and 34, an element OR-NOT 35 and an inverter 36 "

Depending on the magnitude to which the input signal should be limited, the n bits of the input signal bus 28 are divided into two groups: from 1 to (n-m) and from (n-m + 1) to n, and moreover. The first group of bits with

1 to (n-m) is connected to the first input; Dam groups of 30 OR elements, the outputs of which are connected to the first inputs of a group of 31 elements of coincidence, the outputs of which are connected to the (n-tn) lower-order bits of the outputs of block 20 of the limit. The second group of busbar bits 28 s (p-tp + 1) to p is connected directly to the corresponding outputs of the limiting unit 20 and to the m inputs of the AND-NE element 32 and the OR element 3-3, respectively. The output of the element AND-NOT 32 is connected to the first input of the element OR 34, the output of which is connected to the second inputs of a group of 31 elements matching the output of the element OR 33 is connected to the first input of the element OR-NOT 35, the second input of which is connected to the output of the inverter 36, and the output - with the second inputs of a group of 30 elements OR. The second input element OR 34 and the input of the inverter 36 are connected to the bus 29 characters.

Reset node 21, for example, can be implemented as a resistor R and a capacitor C connected in series, the second terminal of the resistor P. is connected to the power supply power supply bus, and the second terminal of the capacitor C to the common bus, the combined terminals of the resistor R and capacitor C are connected to the output of the reset unit 21,

The device works as follows.

After switching on the supply voltage, the reset node 21 generates a signal that sets the counting triggers 4 and 5 and the trigger 25 to zero, builds the coincidence counters 1 and 2 through the coincidence element 11 and then gates the trigger 6 through the inverter 14 having passed through the limiting unit 20, is recorded in the forward (with a positive signal) or in the reverse (with a negative signal) code in counter 1, and the sign code of this signal is recorded in the trigger 6 characters. Depending on the sign of the input signal, generator pulses of 7 rectangular pulses with a frequency f pass through the OR element 15 (positive sign) or through the OR element 16 (negative sign) and are received respectively either at the input of the direct count or to the countdown counter 1 input. Depending on the size of the input signal mantissa on the transfer outputs (either on the forward or reverse) of counter 1 after a period of time

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where n is the number of binary bits

counter;

N - the input number mantissa after the initial setup (gating) a negative pulse appears, which from the output of counter 1, passed through elements 8, 17 and 9, goes to the input of the counting trigger 4 and switches it (

The same impulse, passed through elements 12 and 10, is fed to the input

0

counting trigger 5

and switches b

five

0

five

0

five

0

five

it is time delayed il, with respect to the switching of trigger 4. Time Ј, the delay is determined by the driver of 12 pulses. The direct pulses from generator 7 also arrive at the input of counting trigger 3, which produces a frequency division f. by 2. Square-wave pulses with a frequency of f0 / 2 from the counting trigger 3 arrive at the counting input of counter 2. At the transfer output of counter 2, after a time interval of t -2n + / f0, after the initial setting, a negative pulse appears that passes through element 10 matches, enters the counting trigger 5 and returns it to its original state. The same impulse, passed through the shaper 13 and the coincidence element 9, with a time delay g, determined by the shaper 13, is fed to the input of the counting trigger 4 and also returns it to its original state

Negative impulse output

counter 2 through matching element 11 is gating for counters 1 and 2 and through inverter 14 for trigger 6 of the sign. The process then repeats.

Thus, the device enters the automatic gating mode. At the same time, from the outputs of the pulse-width modulator (bus 26 and 27), there are direct and inverse sequences of pulses with a period T t 2.

 with-. Moreover, taking into account that from trigger 1 to the first input of switch 18

an inverse signal arrives, and from trigger 5 to the first input of switch 19 is a direct signal, then between the fronts of the direct and inverse sequence of pulses a separation of duration Ј and 0g is formed. It's obvious that

t 7 (2 - N) must be greater than / j ,,

otherwise, the pulse-width modulation will fail. To ensure this condition, a limitation block 20 is used which does not allow the input signal to exceed a predetermined value N.ofl. | C

The outputs of switches 18 and 19 are connected to output buses 26 and 27 via matching elements 23 and 24, which block these muds at the time of the appearance at the outputs of a com- at high level signal mutators, which may be caused by an abnormal situation in the device. The outputs of these switches are also connected to the inputs of the NAND element 22, at the output 25 of which a low level signal is generated when two high level signals appear at its inputs simultaneously. The low level signal from the output element AND-NOT 22 is fed to the input of the installation facility in

II, 1

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1 trigger 25 and sets it to

low signal

The level from the inverse output of the trigger 25 is supplied to the second inputs of the elements 23 and 24, at the outputs of which a low level signal is formed, which, if the device operates with a power transistor bridge, prevents an emergency situation with heavy material losses.

Thus, the introduction of two coincidence elements, an NAND element and a trigger into a digital pulse-width modulator allows the device to expand its functionality by using a modulator in devices that do not allow one-time high-level signals on both output buses .

Claims (1)

Invention Formula Digital pulse-width modulator according to auths, R 1478316, characterized in that, in order to increase reliability, it additionally introduces two elements of coincidence, the AND-NOT element and the trigger, the installation input to which is connected to .the output of the resetting unit, the inverse output with the first inputs of the elements coinciding with the jraft, and the installation input into 1 - with the output of the NAND element, whose inputs Connected respectively to the outputs of the switches and the second inputs of the elements of coincidence, the outputs of which are connected to the output buses of the device. && Ю0 | pJf Mmm nm nm + f