SU1631700A1 - Device for digital phase detection of pulse trains at inequal frequencies - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to increase the frequency sensitivity at frequencies that are multiples of the input number. The device for digital / g-g w phase detection of pulse sequences at unequal frequencies contains accumulative adder (NS) 1, digital-to-analog converter (DAC) 2, low-pass filter 3, shaper 4 of the reset signal, first D-flip-flop 5, second D-flip-flop 6, the third D flip-flop 7. In the initial state, the first, second, and third O-flip-flops 5, 6, 7 are in the zero state, and logical units are set at the output of the shaper 4. The device operates in different ways depending on the ratio of the first and second clock frequencies. At tV kf, fT kf and fT kf, the constant component at the output of the DAC 2 is different and depending on the ratio of the frequencies, the order of operation of the first, second and third D-flip-flops is 5-7. The order of their operation is controlled by shaper 4. 4 Il. SO with

Description

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The invention relates to radio engineering and can be used in transceiver and measuring equipment.

The purpose of the invention is to increase the frequency sensitivity at frequencies that are multiples of the input number.

FIG. 1 shows a structural electrical circuit of the proposed device; in fig. 2 - timing work for the case of f k. ft; in fig. 3 - the same. for the case, f k fT; in fig. 4 - the same for the case f k fT.

A device for digital phase detection of pulse sequences at unequal frequencies contains an accumulating adder (NS) 1, a digital to tax converter (DAC) 2, a low-pass filter 3, a shaper 4 of a reset signal, a first O-trigger 5, a second D-trigger 6 , third D-trigger 7.

The device works as follows.

FIG. Figure 2 shows the timing diagrams of the operation in the case where HC1 is two bits. the input number at the numerical input K 3/4 0.112 and the second clock frequency f k fT, where ft is the first clock frequency. NeTrig. 2a and b show the first and second clock sequences, respectively (only the edges along which the triggers and registers switch are marked); in fig. 2 v and d are the sum of the HC 1 and the edges of its overflow signal, respectively; in fig. 2 d, e and g are the states of the first D-flip-flop 5, the second D-flip-flop 6 and the third D-flip-flop 7, respectively; in fig. 2 C and and - signals, respectively, on the first and second outputs of the driver 4.

At the initial moment of time, the first, second, and third D-thringers 5, 6, 7 are in the zero state (the device comes to this state from any other automatically), while the outputs of the former 4 are set to 1. With the arrival of an overflow pulse HC 1, the first D-flip-flop 5 is written to the unit set at its information input. At the same time, the previous state of the first D-flip-flop 5, i.e. the second D flip-flop 6 remains in the zero state. The average frequency of overflows HC 1 is equal to the frequency at the second clock input f. Before the next overflow pulse arrives, an impulse arrives at a frequency f, which sets the third D-flip-flop 7 to one, and then zero and zero levels appear on the first and second outputs of shaper 4, resetting the first 5 and third 7 D-triggers to zero state the At outputs 4, the former 4 is then reinstalled.

FIG. 2k shows the output signal

DAC 2, High frequency fluctuations of this signal are eliminated by filter 3.

FIG. 3 shows the timing diagrams of work at f k fT. The signals here are also indicated as in FIG. 2. At the initial moment of time, the first D-flip-flop 5 is in the single state, the second 6 and the third 7 D-flip-flops are in zero, at the outputs of the former 4 are set 1. With the arrival of the overflow signal from HC 1

the second D-flip-flop b is set to one. If now, before the arrival of the pulse with frequency f, the overflow pulse from NS 1 comes again, the state of the flip-flops does not change. With the arrival of the second clock pulse, one is recorded in the third D-flip-flop 7, which results in a zero level at the second driver output 4, which causes a reset of the second 6 and third 7 D triggers to the zero state, after which the unit 4 is set at the second output of the former 4, after which the process is repeated. At the input of the higher bit of the D / A converter 2, 1 is kept, due to which the constant component of the output signal of the D / A converter 2 is obtained significantly larger than in the previous case.

Due to the non-uniformity of the following pulses of the overflow of HC 1 possible

a situation where two pulses of the output signal are placed between the overflow pulses. In this case, the first D-flip-flop 5 may momentarily drop to zero, however this situation is

rare and does not significantly affect the operation of the synthesizer.

FIG. 4 shows the timing diagrams of the synthesizer when f k ft. The signals here are marked as /, as in

FIG. 2. At the initial moment of time, the first 5 and second 6 D-flip-flops are in the zero state, the third D-flip-flop 7 is in the unit one, at the outputs of the shaper 4 are set 1. With the arrival of an impulse

the overflow from HC 1 to the first D-flip-flop 5 is written to one, which causes the appearance of O on the first and second outputs of shaper 4, which reset the first, second and third D-flip-flops 5,6 and 7 to zero

state, after which the output of the former 4 is set again 1, With this ratio of frequencies before the arrival of the next overflow pulse from the NS 1, a second clock pulse must appear

frequency f, which enters the third D-trigger 7 unit. At the input of the higher bit of the DAC 2, the zero level is almost constantly maintained (with the exception of short units due to switching delays). The constant component of the output signal of the DAC 2 is obtained significantly less than in the first case (Fig. 2).

The imaging unit 4 may be performed, for example, in the form of two AND-NOT logical elements (not shown), the parallel-connected first inputs of which are the first input of the imaging device 4. The second input of the first AND-NE logic element is the second input of the imaging device 4. Parallelly connected the third input of the first NAND logic element and the second input of the second NAND logic element are the third input of the driver 4. The outputs of the AND-NE logic elements are respectively the first and second outputs of the driver 4.

Claims (1)

Apparatus of the Invention A device for digital phase detection of pulse sequences at unequal frequencies, comprising a series-connected accumulating adder, a digital-to-analog converter and a low-pass filter and a first trigger, the clock input and output of which are connected respectively to the overflow output of the accumulating adder and to the input of the higher digit digital - a gob converter, with the clock and numeric inputs of the accumulating adder being the first clock and numerical inputs of the device for digital phase detection of pulse sequences at unequal frequencies, characterized in that, in order to increase the frequency sensitivity at frequencies multiple to the input number, the first trigger is designed as a first D-trigger, and a second D-trigger is introduced, the third D-flip-flop and shaper of the reset signal, the first input of which is combined with the information input of the second D-flip-flop and connected to the output of the first D-flip-flop, the second and third inputs and the first shaper of the reset signal oedineny respectively with output of the second D-flip-flop. the output of the third D-trigger and the installation input of the first trigger, the second output of the reset signal generator is connected to the installation input of the second D-trigger and to the installation input of the third D-trigger, the clock input of the second D-trigger is connected to the overflow output of the accumulating adder, the third input clock D-flip-flop is the second clock input of the device for digital phase detection of pulse sequences at unequal frequencies. a) I I I I I I I I I .1 I I 1 b) ЈI I I I I I I I t GP P P P P P P P PG I I I I I I I I -.one. .1 J.. TT . k) DAC nrJLrLnrJlJln -rlr f xf, FIG. 2 a) 1-I- I i 1 1 I b) -J II- c) S d) P d) " e) vg g) OS h) U and) Lz f ll FIG. Uh (I 1L 3) Li LJ.J and) U L TTTGL.-L-.TJ-J7.r. ) PAP txb U Ju j I I I I I I I I I I I I