SU1629906A1 - Device for regulation of power - Google Patents

Abstract

The invention relates to electrical engineering and can be used. for AC power control. The aim of the invention is to improve the accuracy of output power control when operating on a resistive load. The goal is achieved by introducing into the device an additional driver 4 sync pulses, a reversing counter 6 and a buffer register 7, with information inputs connected to the power reference source. The required accuracy of the power setting is determined by the division ratio of the counter 6 and the number of bits of the register 7. The operation of the device consists in passing or eliminating half-periods of the current to the load using the thyristor unit 1. The frequency of excluding half-periods of the current into the load is inversely proportional to the code value from the output of the register 7, which is determined by the code received from the source of the power reference, Thus, depending on the reference signal, the power transmitted from the source 2 of the alternating current to the load may change value from maximum to zero, 2 Il. ate

Description

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The invention relates to electrical engineering and can be used to regulate the electric power of alternating current.

The purpose of the invention is to improve the accuracy of adjusting the output power when operating at a resistive load.

Fig. 1 shows a block diagram of a device for adjusting the power of an alternating current; Fig 2 shows timing diagrams for the operation of the device,

The device (FIG. 1) contains a thyristor unit 1, the power input of which is connected to the terminals for connecting the alternating current source 2, and the output to the terminals for connecting the load, the driver of the 3 clock pulses and the additional generator of the 4 clock pulses, the output connected to the sync pulse the trigger input 5, the information input of the trigger 5 is connected to the output of the reversing counter 6, the information inputs of which are connected to the outputs of the buffer register 7, the setup input to the N-th high register bit 7, the summing input d - conclude formiro

the clock 3 clock pulses, and the sync input to the output of the element And 89 the first input of which is connected to the output of the driver 3 clock pulses, and the second input with the inverse output of the trigger 5 connected to the control input of the thyristor unit 1, the inputs of the formers 3 and 4 are connected to the terminals for connecting the AC source0 The information inputs of the buffer register 7 are connected to the terminals for connecting the source of the power reference0 When the current passes through zero (Fig. 02a) from the AC source, the driver 3 is synchronized mpulsov performs formation of a pause (fig02b) and an additional clock generator 4, of a pulse (Figure 2B), the duration of which Men Chez pause formed formirovatelem0

The device operates as follows.

From the source of the power setting, which can be used as a temperature sensor with a digital output connected to the load, or in the simplest case, a set of codes, the code of the power required for transmission from the AC source 2 to the load is recorded in a buffer mode.

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Spark 1, Shaper 3 sync pulses at the appropriate point in time generates a signal (Fig. 26), which enters the summing input of counter 6 and increases the previous value of this counter by the presence or absence of a signal. Overflow of counter 6 is recorded on the sync pulse from the output of synchro 4 in trigger 5 (fIGo2g} 0 When a signal is present, the Overflow trigger 5 is set to O, turns off the thyristor unit 1 for the time of one half-cycle of alternating current (FIG. d) and sets the resolving potential to m input of AND 8o By decline signal output from the clock shaper 3 and soot- - respectively, the second inlet member 8 and the code output from the output buffer register 7 is written into the counter 6 "overflow frequency signal generating counter 6, and

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accordingly, the frequency of excluding half-periods of the current in the load is inversely proportional to the code value from the output of the buffer register 7, and since the code from the output of the buffer register 7 can change its value from zero to maximum, the power transmitted from the AC source 2 through the thyristor unit 1 changes It has its own value from maximum to zero. To evenly exclude a certain number of half-periods per unit of time from the continuous flow of current half-periods, the output connection of the buffer register 7 with information ion counter input 6 is formed as follows; the first low-order bit of the buffer register 7 is connected to the (M-1) th high-order bit.

the t counter, the second bit d - c (N-2) -M bit, the third bit d - c (M-3) m ..., (Y-1) th bit d - with the first younger digit of the counter 60

Let us assume that the load needs to deliver the full power in this case, from the source of the power setting, the buffer register 7 receives such a code, which provides Log 1 at the highest register de register 7, and therefore, at the installation input of the counter 6, as a result counter 6 stops summing the 3 sync pulses arriving from the generator and at its output will be set Log01 o This Log „1 sync pulse

Som from the driver 4 output will be recorded in trigger 5, as a result of which inverse inversion is set to Log „0, which will maintain the thyristor unit 1 in open state. To supply power to the load equal to 99%, the counter overflow signal 6, t. e „Log„ О, will be generated by the 100th sync pulse of the former 3 “The sync pulse from the former 4 will write this into the trigger, which will turn off the thyristor unit 1“ Thus, if you set 99% of every 100 half-periods coming from source 2 into the load, the device will be alone

To deliver a power equal to 98% to the load from the source of the task, a code enters, after which it is written into register 7 and then into counter 6 from the stream of power half-periods coming from source 2 to the load, the device will cyclically exclude every 99th and t0d „

The required accuracy of the power setting is set by the corresponding dividing ratio of the counter 6, for example, when the dividing ratio of the counter 6 is 100, the accuracy of the power setting is 1% of the maximum when the ratio is 1000 - 0.1% and so on, while the buffer register 7 increases on four do of the buffer register, and information

bit (when using binary-decimal counters 6)

Thus, the introduction of an additional sync pulse generator 4, counter 6 and buffer register 7 with the number of bits required with the required power setting accuracy and with corresponding connections with the rest of the circuit elements provides an increase in the output power accuracy and elimination of high-frequency interference by turning on the thyristor unit 1 at zero current in load

The invention involves the connection of a resistive load, t „e0 relative to inertial converters of electrical energy into heat, light, for example heaters, electric lamps and cores.

inputs to the outputs of the buffer register, while the bits of the reversible counter are connected to the bits of the buffer register in reverse

40 ke, the information inputs of the buffer register are pinned to the input pins for connecting the source of the power reference, in addition, a trigger is used as output

45 inverse output, a node is used as a sync pulse generator that pauses when a current passes through zero from the alternating current source,

50a as an additional sync pulse generator is a node that at this moment generates a pulse, the duration of which is a small pause generated by the sync pulse generator

Claims (1)

Claims An AC power control device comprising a thyristor unit, the power input of which is connected to the terminals for connecting an alternating current source, and the output to the terminals for connecting a load, the driver of sync pulses, the input of which is connected to the terminals for connecting the AC source, and output with the first input of the element I, the second input of which is connected to the trigger output, about 5 tons and 5, so as to increase the accuracy of the output power control when working on the asset additional load, an additional v is inserted into it (li nelny shaper clock pulses} 0 N-bit dmny buffer register and (N-1) - bit reversible counter, the input of the additional clock generator connected to the terminals for connecting the AC source 5 current, and the output to the synchronization input of the trigger, the information input of which is connected to the output of the reversible counter, and the output to the control input of the thyristor loop, 0 the synchronizing input of the reversible counter is connected to the output of the element I, the summing input to the output of the clock generator, the setting input to the M th high section of the buffer register, and the information inputs to the outputs of the buffer register, while the counter reversing counter is connected to the bit the buffer register in reverse order, the information inputs of the buffer register are pinned to the input pins for connecting the source of the power reference, in addition, its output is used as a trigger an inverse output, as a generator of clock pulses, a node was used that forms a pause when a current passes through zero from an AC source, and as an additional clock generator, a node that at this moment generates a pulse, the duration of which is a small pause, formed by the clock generator but i Tj ir rnrnrn.rirnr ijrTr p p p p p p p p p p p FIG. 2