SU1626444A1 - Electronic commutator - Google Patents

Abstract

The invention relates to electrical communication technology and can be used in automatic switching systems. The aim of the invention is to reduce the connection establishment time by determining the state of the channels in the lines of the pulse code modulation. The electronic switchboard contains the block 1 setting the format of the input data., The block 2 of the data memory, the multiplexer 3 outputs, the block 4 sets

Description

The invention relates to electrical communication technology and can be used in automatic switching systems.

The purpose of the invention is to reduce the connection establishment time by

determining the state of the channels in the pulse code modulation lines.

FIG. 1 shows a block diagram of an electronic switch: in FIG. 2 is a control block diagram; Fig. 3 is a block diagram of the data collection of the incoming channels; FIG. 4 is a block diagram of the data collection of outgoing channels; Figs 5-19 show command execution algorithms.

The electronic switchboard (Fig. 1) contains the input data setting unit 1, the data storage unit 2, the output multiplexer 3, the output data setting unit 4, the buffer driver 5, the first address multiplexer 6, the connection memory unit 7, the buffer register 8 , second address multiplexer 9, controller 10, control unit 11, first counter 12, key AND block, second counter 14, incoming cap data acquisition unit 15, outgoing channel data acquisition unit 16, additional connection memory block 17, register 18 output, register of 19 commands, input bus 20 given bus, data output bus 21, access bus 21.

The control unit 11 (Fig. 2) holds the 2J fixed memory, the microprogram control unit 24, perg, the buffer buffer register 23, the pryv 26 and the second 27 Andy, iput r 28 address, re0

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output address master 29, first 30 and second 31 elements of the comparison, first counter 32 channels, second additional buffer register 33, input address register 34, decoder 35, clock counter 36, first 37 and second 38 triggers, read resolution trigger 39, first 40, second 41, third 42, fourth 43, fifth 44, sixth 45, seventh 46, eighth 47 and ninth 48 inputs, first 49, second 50, third 51, fourth 52, fifth 53, sixth 54, seventh 55 , the eighth 56, the ninth 57, the tenth 58, the eleventh 59, the twelfth 60, the thirteenth 61, the fourteenth 62 and the fifteenth 63 exits.

The blots 15 of the data collection of the incoming channels (Fig. 3) contain the third 64 and four. vert 65 triggers, first shaper 66 of occupancy code, first counter 67 free channels, second counter 68 channels, first address register 69, third element 70, first 71, second 72, third 73 and fourth 74 ventilation circuits, first 75, the second 76 and the third 77 entrances, the first 78 and the second 79 from each other.

Block 16 of the outgoing channels data collection (Fig 4) contains the fifth 80 and sixth 81 triggers, the second occupier 82 of the occupation code, the second counter 83 of the free Kachalov, the third counter 8 + channels, the second address register 85, the fourth element And 86, the fifth 87, the sixth 88, the seventh 89 and the eighth 90 valve circuits, the first 91, the second 92 and the third 93 inputs, the first 94 and second 95 outputs.

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The switch works as follows.

The switch can operate in three modes: establishing a connection (free, group and linear search for both information inputs and outputs); disconnection; transit mode, by commands, the execution algorithms of which are shown in FIGS. 5-19.

Consider the algorithm for establishing a connection in an electronic switch with a linear search in the connection establishment mode (Fig. 8).

From the beginning of the pulse-code modulation cycle, a cycle clock pulse arrives at the input of the SRC unit 11, which sets all counters of the electronic switch to the zero state, and the second flip-flop 38 sets it to one state, the output of which is fed to the first input of the register shift of command 19 .

Writing into the command register 19 is effected until the moment when the second trigger 38 switches to the zero state with a signal from the corresponding output (1y) of the decoder 35.

In the register 19 of commands on the bus 20 data input receives the appropriate control command,

From the third output of the register 19 of commands on the top of the input 44 of the control block 11, the operation code of this command enters the microprogram control node 24, which sets the starting address of the program for executing this command, stored in the node 23 t,

In accordance with the received address from the node 23 of the permanent memory, the block control signals are read out.

From the fifth outputs 53 of the block 11, the signals go to the write enable inputs (read from the memory block of the connection 7, and simultaneously from the ninth output 57 of the block 11, a read enable signal is sent to the first input of the command register 19. From the first output of the command register 19 to the first input 75 block 15 and the input of the first register 69 of the address receives the address of the incoming channel, and the second counter 68 channels zeroes

Similarly, from the second register 19 of commands, the address of the outgoing channel enters the second register 85 of the address of block 16. The third counter of the 84 channels of block 16 is zeroed.

Simultaneously, from the thirteenth 61st and twelfth 60th outputs of block 11, the enable signals recording the gates of storing information into the corresponding elements are sent to the third write inputs of the first 69 and second 85 address registers, respectively, through the second inputs 76 of the block 15. and the third inputs 93 of the block 16

Second beat The first input of the register of 19 commands receives a prohibiting signal from the ninth output 57 of the block 11.

The control inputs of the third 73, fourth 74, seventh 89 and eighth 90 valve circuits, respectively, from block 15 and 16, receive the enable signals from the thirteenth 61 and twelfth 60 outputs of the control block 11;

Through the fourth 74 and eighth 90 valve circuits, respectively, the bus addresses of the incoming and outgoing channels from the first 69 and second 85 address registers receive log, n and

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logg ha, respectively, of the higher rasl-electronic switch and the address is barely 45 D ° to addresses (and log, ha are the codes of the parent microcommand, which is executed similarly after the current microcommand is completed. The address of the next microcommand can be changed according to the results of the next microcommand, which come from the corresponding blocks of the electronic switch on the second 41 and seventh 46 inputs of the block 11.

In accordance with the command execution algorithm (for example, the fourth one, Fig. 8), subroutine 1 (Fig. 18) and subprogram 2 (Fig. 19) begin to run simultaneously.

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measures of incoming and outgoing group paths - PCM lines included in the information inputs and outputs of the electronic switchboard).

The third 73 and seventh 89 valve circuits, respectively, receive the log2M address bits of the incoming and outgoing channels and log2M lower address bits (log / jN and log2M and codes for the number of channels in the incoming and outgoing group cycles — PCM lines included in information inputs and outputs of the electronic switch).

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From the fifth outputs 53 of the block 11, the signals go to the write enable inputs (read from the memory block of the connection 7, and simultaneously from the ninth output 57 of the block 11, a read enable signal is sent to the first input of the command register 19. From the first output of the command register 19 to the first input 75 block 15 and the input of the first register 69 of the address receives the address of the incoming channel, and the second counter 68 channels zeroes

Similarly, from the second register 19 of commands, the address of the outgoing channel enters the second register 85 of the address of block 16. The third counter of the 84 channels of block 16 is zeroed.

Simultaneously, from the thirteenth 61st and twelfth 60th outputs of block 11, the enable signals recording the gates of storing information into the corresponding elements are sent to the third write inputs of the first 69 and second 85 address registers, respectively, through the second inputs 76 of the block 15. and the third inputs 93 of the block 16

Second beat The first input of the register of 19 commands receives a prohibiting signal from the ninth output 57 of the block 11.

The control inputs of the third 73, fourth 74, seventh 89 and eighth 90 valve circuits, respectively, from blocks 15 and 16, receive the enable signals from the thirteenth 61 and twelfth 60 outputs of the control unit 11;

Through the fourth 74 and eighth 90 valve circuits, respectively, the bus addresses of the incoming and outgoing channels from the first 69 and second 85 address registers receive log, n and

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measures of incoming and outgoing group paths - PCM lines included in the information inputs and outputs of the electronic switchboard).

The third 73 and seventh 89 valve circuits, respectively, receive the log2M address bits of the incoming and outgoing channels and log2M lower address bits (log / jN and log2M and codes for the number of channels in the incoming and outgoing group cycles — PCM lines included in information inputs and outputs of the electronic switch).

i. bus addresses of incoming Kachalov n, i address input of an additional block i z 17 of the connections memory receives the input channel signals.

11.1 the control input of the second multiplexer q of the address comes sigpa- 1Y from the output of the second counter 14, the input of which receives the clock pulses T.

The clock pulses at the control input of the second multiplexer 9 address provide the output at its output and, accordingly, the address input of the block of the address of the outgoing channel from the pin of the address of the outgoing channels.

From the fifth 53 and sixth 54 B GKDOV of the Unit 11, the read inputs for the multi-bus buses are sent to the control inputs of the read register of the connection memory block 7 and the additional block 17

From the data output of the additional G: about 1 7 memory of connections, information about the state of the incoming channel selected at the received address is fed to the counting input of the first counter of 67 free channels.

In case the channel is free and third; trigger b4 is set, then its single signal goes through the second input 41 to block 11, which increments the contents of the first free-channel counter 67 via the first input 75 of the incoming data collection block 15 to the channel, in which case the channel is occupied, the increment does not occur, At the same time and similarly, the state of the outgoing channel is checked and, accordingly, the second counter is incremented by 83 free channels of block 16 according to the signal from the thirteenth output 61 of block 11, if this outgoing channel is free the fifth trigger 80 is set. The relay channel is busy; the increment does not occur.

If the third 64 and fifth 80 flip-flop are not installed, and the corresponding cable is free, then the trigger is set by applying to its first input a state signal from the outputs of the corresponding blocks 7 and 17 through the second 92 and third 77 inputs of blocks 1 and 16. From block 11 The write enable signal is sent to the first 69 and second 85 address registers (this signal comes in when the CTIVMICH command is executed, (connection)

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the corresponding first 67 spikes of the second 83 free channel counter are incremented

If the contents of the second 68 and third 84 channel counters of blocks 15 and 16 are less than the number of time channels in the group PCM paths included in the information input and output of the electronic switch, respectively, then the signal from block 11 increments them and the described second cycle procedure repeats

If the contents of the second 68 and third 84 channel counters become equal to the number of channels in the group PCM paths included in the information input and output of the electronic switch, respectively, a signal is generated at their overflow outputs, which goes to block 11, and the next tact work

The third beat. The enable signal from the ninth output 57 of the block 11, which arrives at the first input of the register 19 of commands, from its first output via the address bus to the second data input of the block 7 and the address input of the additional block 17 receives the address of the incoming channel, and from the second output register 19 of commands via the address bus of the outgoing channels to the second data input of the additional block 1 7 and through the first multiplexer 6 of reading the address and; the address input of the block 7 receives the outgoing channel C of the pint 53 and the sixth 54 outputs of the block 11; the blocks 7 and 17 receive read enable signals.

Similarly to the second clock cycle, the state of the channels in the third 64 and fourth 65, fifth 80 and sixth 8 triggers of blocks 15 and 16 is memorized.

Fourth cycle In case the third 64 and fifth 80 triggers are set (channels are free), then the signal from their outputs in block 11 through the second 41 and seventh 46 inputs, the last generates a write enable signal pa blocks 7 and 17, the first inputs of which are signals for the occupation of connected cabals. When this happens, the source of the outgoing channel is dropped into the first area of block 7, and the address of the incoming channel is dropped into the second area. Similarly, in the per-pvK area of the additional block 17

the state of the incoming channel is recorded through the first data input, and in the second area, the address of the outgoing channel3

From the twelfth 60th and thirteenth 61 outputs of block 11, the corresponding bits of the multi-bit bus connect the first 67 and second 83 counters of the free channels to the counting inputs of the signal, reducing their content by one.

Thus, the connection between the specified channels is established.

Fifth time. In case the connection is established, by the enable signals from the twelfth 60 and thirteenth 61 outputs of block 11 supplied to the control inputs of the third 73, fourth 74, seventh 89 and eighth 90 valve circuits, and the write enable signal supplied to the first and second inputs the output register 18, from the address registers 69 and 85, the addresses of the channels between which the connection is established are recorded.

The sixth beat. According to the signals from the outputs of the third 64 and the fifth 80 flip-flops to the inputs of the address 66 and the second 82 shapers of the busy code, the signals from block 11 fed to the read enable input, and the enabling signal sent from block 11 pl 71 and fifth 87 valve circuits, as well as the write enable signals from block 11 supplied to the controlling third and fourth inputs, write to the output register 18 of the occupancy or free codes, respectively, of the first 66 and second 82 quantities free one incoming and outgoing channels from the first 67 and second 83 free-channel counters.

Seventh beat. By enabling the signal from the ninth output 57 of the block 11, arriving at the first input of the register of 19 commands and the ninth input of the register 18 of the output, the operation code is rewritten from the register of 19 commands and the register 18 of the output

This completes the establishment of the connection and the formation of a message about the results of the execution of the command. The following is the output of the results.

Under the action of the shift resolution signals and clock signals Tr, 0

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stepping from block 11 to the output register 18, from the output of the extreme bit (sequential data output), the recorded message is output from the electronic switch. Thus, the command execution cycle is completed and you can proceed to the execution of the next command.

Consider the disconnection process using the example of the fifth command (FIG. 9).

Writing the command to the command register 19, sequential sampling of microinstructions in block 11 occurs as described for the previous command,

In accordance with the command execution algorithm (FIG. 9) and the received address from the permanent memory node 23 (as a result of the decoding of the operation code), block 11 outputs the following signals

First tact. The authorizing signal from block 11 supplied to the first input of the register 19 of commands from its first output to the input of the first register 69 of the address (the first input 75 of block 15) and to the address input of the additional block 17 receives the address of the incoming channel that needs to be disconnected.

The signal from block 11 from the output of the additional block 17 reads the address of the outgoing sweep to which this incoming is connected and enters the first input 91 of block 16.

The authorizing signal from block 11 supplied to the control signals to: the codes of the first 69 and second 85 address registers records the addresses of the incoming and outgoing channels, respectively.

Second beat According to the signal from block 11, supplied to the control inputs of the third 73, fourth 74, seventh 89: f ccms /: 90 valve circuits from the corresponding first 69 and second CRO 85 address registers of these blocks through the first output: - 78 and 94 blocks 15 and 16 channels, respectively, read the addresses of the incoming and outgoing channels that need to be disconnected from

The address of the incoming channel is fed to the address input of the additional block 17, and the address of the outgoing channel through the first multiplexer 6 reads the address to the address input of block 7.

According to the recording resolution signals and the disconnection signal supplied to the fourth and second inputs, respectively, of block 7 and additional block 17, the state is recorded - P). disconnection, respectively, in the first areas of block 7 and additional block 17.

Thus, the address of the outgoing channel to which the specified incoming channel was connected was determined, and these channels were disconnected.

According to s: from block 11, input to the setup of the fourth 65 and sixth 81 flip-flops, these triggers are set and signals from their outputs prevent the control signal from block 11 from passing through the third 70 and fourth 86 elements And to the recording enable input of the first and second 85 address registers.

Subsequently, subroutine 1 (Fig. 18) and subroutine 2 (Fig. 19) are executed simultaneously in accordance with the actions described in the execution of the previous command.

The third beat. After the subprograms I and 2 have been executed, a sequential pi result is performed; This is done in the same way as described for the previous command by reading (rewriting) the first 66 and second 82 occupants of the busy code, the contents of the first 67 and the third 83 free channels, first 69 and the second 85 registers of the address and operation code from the third outputs of the register of 19 commands to the register of 1 input and shift information to 18 output.

In the transit operation mode of the electronic switch, the input data format setting unit 1, data storage unit 2, output multiplexer 3, output data setting unit 4, buffer driver 5, first address multiplexer 6, buffer register 8, memory block 7 are used.

tons of connections, the second multiplexer 9 addresses, the first 12 and second 14 counters and the controller 10.

At the same time, we consider that all the required connections are established and no disconnections occur. Information goes to the n inputs of block 1 of the task

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format of data for group paths of PCM. Block 1 is used for additional temporary compaction of incoming PCM group paths into one path.

The data memory block 2, the data input of which receives information from the output of block 1, writes in consecutive cycles in successive cells addressed by the second counter 14 (clock; the frequency supplied to the first counter is 2 times above the frequency of the time signals in the compressed path), during odd clock cycles, the addresses of the readable cells are set by reading the contents of the buffer register 8 through the second multiplexer 9 of the iia address address input of the block 20

The information read from block 2 retreats through a multiplexer 3 outputs to block 4 and specifies the output data format, which sums out the outgoing group paths by decompacting with

Formed group paths arrive at the inputs of the buffer driver 5 and further to the information p. electronic switch in the presence of enabling signals coming from the buffer register S through the controller 10o

JJ buffer register 8 connection status information and time slot addresses are read from connection block 7 into even numbers.

The read control from block 7 is carried out by transmitting information from even the first counter 12 through the first multiplexer 6 to read the address to the address inputs of the block 7t. The key block 13 is closed during the even clock by the control signal from the first counter. 12, thereby prohibiting the transfer of information from the second data output of lock 7 to the incoming address address bus. In odd cycles, block 7 is accessed when operating in the switching mode (connecting and disconnecting).

Block 11 works as follows. The access bus 22 connects the control unit 11 to the control unit. the device of the system in which this splendid so is used; gutator

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13

The bus is available bidirectionally time division.

Consider the process of entering the contents of the channel into the access bus (command 10, Fig. 14). The command register 19, via the data input bus 20, receives a command to connect the specified PCM channel to the access bus 22 via an electronic switch.

The operation code of the command is decoded in the microprogram control unit 24 of block 11, from which a write enable signal is emitted to the control input of the input address register 34. At the same time, from the first output of the register 19 of commands, the address of the channel is written to the register 34 of the input address, the contents of which are to be entered into the access bus 22, "

The channel address from register 34 enters the second input of the second comparison element 31 and is compared with the addresses of the outgoing channels, which correspond to the alternately incoming codes from the output of the first counter of 32 channels.

When the address codes match, the second comparison element 31 generates a signal arriving at the input of the shift resolution of the second additional buffer register 33. at the same time, from the output of the block 2 of the data memory, in clock cycles arriving at the third input (Ti) of the second additional buffer register 33 rewrites the contents of the selected temporary channel.

From the second additional buffer register 33 to the access bus 22, information is read on the enable signal, which arrives at its control input through the second element 27 from the output 1 of the decoder 35.

When recording information from the access bus 22 to a predetermined PCM time channel, the electronic switch command register 19 over the data input bus 20 receives a command to connect the access bus 22 to the specified PCM channel in this time channel.

The operation code of the command is decrypted by the firmware control node 24, and a write enable signal is output to the output address register 29. At the same time, from the second output of the register 19 of commands, the address ka10 is written into the register 29 of the output address

4644414

information in which to enter information.

The channel address from the output address register 29 arrives at the second input of the first comparison element 30 and is compared with the addresses of the outgoing channels, which correspond to the successively incoming codes from the output of the first counter of the 32 channels.

When the address codes match, the first comparison element 30 generates a signal, which is input to the shift resolution of the first additional

15 of the buffer register 25. At the same time, the information from the output of the additional buffer register 25 through the multiplexer 3 of the output is read into the specified channel of the compressed group

20 tract.

Information is recorded in the first additional buffer register 25 from the access bus 22 according to the write enable signal received from

25 output 1 decoder 35.

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Claims (1)

Invention Formula An electronic switchboard containing sequences for the connected input data setting unit, data storage unit, input multiplexer, output data format setting unit and buffer driver, connected in series to the control inputs of the first address multiplexer, connection memory unit, buffer register and a controller, a control unit and the second multiplexer of the address that is connected; the address inputs of the data storage unit whose output is connected to the first input of the control unit, and the second output of the buffer register is connected to the first input of the second address multiplexer, characterized in that, by reducing the connection time, by determining the state of the channels in the line:; impulse-coded modulation, the first counter, the output of which is connected to the first input of the first multiplexer of the address, the key block, the output of which is connected to the second input of the connected memory block, and the input data acquisition unit of which the second input connected to the second input of the control unit 15 the second counter, the output of which is connected to the second input of the second multiplexer of the address, the serial data collection unit of the outgoing channels, the second input of which is connected to the first output of the memory block of the connections, and the additional memory block, the first input of which is combined with its first output, command register and output register, the first, second, third and fourth inputs of which are connected respectively to the first, second, third and fourth outputs of the control unit, the fifth, sixth, seventh and eighth outputs of the cat The first is connected respectively to the third and fourth inputs of the connection memory block, the second and third inputs of the additional connection memory block, the fourth input of which is combined with the second input of the connection memory block, the fifth input of the output register, the third input of the control unit and connected to the first output commands, the second output of which is connected to the first input of the additional memory block of connections, the second input of the first multiplexer, the sixth input of the output register and the fourth input of the control unit, the ninth and de fifth outputs which are respectively connected to first and second inputs of the instruction register, the third output is connected to the fifth and seventh control input of output register unit entry, the outputs of which are bus EYVO 2644416 Yes device data, input data bus, which is the third inputs of the command register, the fourth input of which is the clock input of the device and combined with the first inputs of the first and second counters, the sixth input of the control unit and the eighth input of the output register, the ninth input 10 of which is connected to the eleventh output of the control unit, the twelfth and thirteenth outputs of which are connected respectively to the second input of the data collection unit of the incoming channels 15 and the third input of the data collection unit of outgoing channels, the second output of which is connected to the seventh input of the control unit, the fourteenth and fifteenth outputs of which are connected 20, respectively, with the second information and control input of the output multiplexer, and the second output of the connection memory block is connected to the second input of the key block, the first input 25 of which is connected to the third input of the data storage unit, the control inputs of the first and second multiplexers of the address and the buffer register, the second output of the additional 30 of the memory block of connections is connected to the third input of the data acquisition unit of the incoming channels, and the second inputs of the first and second counters and the eighth input of the control unit are input clock synchronization, the ninth inputs of which are access bus terminals. fo.-g Team I Subprogram I; Subprogram 2 Yes (Block 67) (Block 67) - I I (Block 83} (Block 83} - I . . Address Bus (Register 69) - -input channels Address Bus (Register 85) - downstream channels one Record 6 P and 1 areas of block 17; P and I areas of block 7 (Register 69) - (Register 18) (Register (Register 18) (Block 67 - (Register 1Y (Block 66) (Register 18) (from the output of the block HF- Register (Block 83 - (Register 18 (Block 82) - (Register 18 ((Register 1fyy ° Yes Reset The end of FIG. five WITH Team 2 Subprogram I; Subprogram 2 i  Tire - / RRGIOTP register 19) - addresses; / TP ° 01  ВЈ2Жх Жо 1 5 / iЈLU (l Clok area (Block 80) T (Register B9 - -111 address from incoming channels (Register 85) Address Bus VV ISPHOES TO: outgoing channels I Write to I and P areas of block 17; I and P blog area 7 I 1 (Block 67) (Block 67) - I (Elok 83) (Klok 83) - I (Register (Register 18 (Register register 18 E ok 67 Register 18) Block 83) (Register 18 Block 66 (Register 18) Block 82 - Register 18 (3 output of block 19) - Register (Register 18) data output I Reset I The end of FIG. b Team 3 J Subprogram I; Subprogram 2  1Li1Ha U Register BF (Register 19) - alresa ,,. (LOCK 17 i (i block area (Block 64} / Rechisto 69 - Tire adress,. MLipo / incoming channels % Bus address  ° GISTR ISHOPYAPIKH K, outgoing channels I  Jani.c I and 11 areas of block 11 1 and 11 areas of block 7 I (D) l about 67 67 - I FLSK 83) L3 - I (° ogistr (Register W) (. Registry B5) - (Register IV)) Block 67 - (Register 18 (.Gun U3 (Register 1B (& block)) - (Register JJ (jack V (Register 1H (3 output of block 19) (Register (Mr. Hygister 1SNI-hLVODV Tnss ( J Team 4 D I Subprogram I; Subprogram 2 I 19 hours reg. 84  M / VnriCIMM / V / K P r-tf Ј c. outgoing (Block b) - channels- (block 7) .HRT "" .about. 17) one 1 area of block 7) - (Block 8f (I area of block 17) 64 T 1Free / registto AgwuinHa addresses of the OS / L channel register (Register 8 aYa geca cxo ± entry in I and P block 17; I and P areas of block 7 one (Block 67 (Plock U3 (Block 67 - 1 (Block 83 - I (Register 69 XPRegister 18 (Register 05) - (Register 18) (Block 67) Regig. Tr 18) Elik B3 - Register 18) (Unlock 60 - (Register 1c (Glock L2 - (Register 18) (3 output of block 19 - Register i (Register 1B)) Yes data i Reset WITH 1 (man J Zig eight FIG. 9 FIG. ten FIG. II FIG. 12 WITH Team 9 I (I output register 19) - Block 34 Setting the trigger 39 I Block 34) 1 output block 31 (Block 32) (2 input block 31) The resolution of the shift block 33, the input is allowed {Shift block output block 33 a record {Output of block 2) - “- (block 33 Shift T0 Tu + I ) Not I Llock 32) flock 32 + I Reading (block 33) Access bus FIG. 13 Team 103 (2 register output 1 - / Block 29) Trigger Setup 28 (block 29) -Xl block input ZF (Block 32) X2 block input 30 fla The resolution of the shift in block 25 I Block 25) block input 3) one Thats tu + i Not (Block 32) (Block 32) + I FIG. 14 Team II) Resetting trigger trigger 39 for reading the second buffer register 33 Gkonets) FIG. 15 FIG. sixteen I Number of incoming / 1 tr ktpvb P Record of the disconnection state in the I area of block 7 (Block 68 (block 68) + I Number  channels in (Block 68) - group inputs L I. + I Not I tsch9oServing 0 one Record of the disconnection state in the I area of block 17 (Block 84) Block 84) + I OS I Team 13 4Ш the end FIG. 17 Subprogram I I 19 Junior Channels (  chik 68 ± Older ones , discharge. Register BE / dBlock 74 / Tire address l (BbNBlock counter in (l block 7 area) (, Block 00 Return from subroutine Block 84) Block 84) + I FIG. 18 Podprgch frame 2 Bus y (Register (2 output. Addresses85 register 19 / - 1Cih outcome, Junior channel channels .CHICK Older bits (Register 8ENblok | sa (Counter 84Nbol ZU "G (I area of block 1) - (Block 64) State 64 - Free Block 67 (Block 67 + I Return from subroutine FIG. nineteen T Block 68 (Block 68 + I