SU1626431A1 - Frame synchronization device - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to increase the noise-tolerant hygroscopic synchronization. contains binary signal receiver 1, receiver cyclic distributor 2, correlation detector 3, control node 4, counter 5, A / D converter 6, threshold unit 7, controlled multivibrator I, pulse front separation unit 9, controlled delay line 10, switch 11 and Mr 12 grid frequency. 3 of this device, the longer the logical 1 is at the output of the threshold unit 7, the higher the clock frequency at the third input of the control unit 4. This achieves an increase in the accuracy of the calculation of the correlation function to compensate for the degradation. the quality of the communication channel in order to increase the likelihood of detecting a sync signal, which ultimately enhances the room; v steady i frame synchronization. Instructions on PP. 2-4 files are distinguished by unit 4, detector 3 and line Yu, their silt is given. 3 etc f-ly, 4 ill. SS 1sl

Description

The invention relates to telecommunications and is intended for use in synchronous data transmission systems.

The purpose of the invention is to improve the noise immunity of cyclic gynchronization.

FIG. 1 shows the structured electrical circuits i of the frame alignment device; in FIG. - control node diagram; and t FIG. 3 is a diagram of the correlation notch mountain; in fig. 4 shows a controllable delay line.

The synchronization cyclone device contains a receiver 1 binary signals, peak p, i is detected (ii unit 2, correlation detector 3, control node 4, counter 5, analog-to-digital converter (A1 P) 6, threshold block 7, controlled multivibrator 8, pulse front selection unit 9, controllable delay line 10, switch 11 and grid generator 12. The control V3eji contains an RS-tripper 13, a key 14, an information reading unit 15 and a permanent memory unit 16. The correlation detector contains shift register 17, multiplication unit 18 and summation unit 19.% praich EMA delay line comprises a shift register 20 and the switch 21.

ABOUT

Yu

O5

Ј

00

The frame alignment device operates as follows.

The frequency ratings of the pulse sequence of the series that forms the frequency grid of the frequency grid generator 12 are selected according to the Kotelnikov sampling theorem for sampling the signal from the communication channel, with the minimum frequency n frequency grid for the tone frequency channel being 8 kHz. In the initial state at the output of the threshold block 7, logical O, the controlled multivibrator 8 is in the standby mode (no generation of pulses), and the counter 5 is in the zero state, i.e. in all its bits logical O, which corresponds to the following; the switch 11 to the third input of the control unit 4 is connected from the frequency grid generator 12 a tap with a minimum pulse frequency; in the controllable delay line 10, the maximum delay value is set, equal to the receiver receiving time 1 binary signals t-1 of binary symbols from the communication channel, where t is the length of the information block in bits. The structure of the transmitted data but the communication channel is an interlace (n + m) of binary signals, where n is a sync signal (sn snrocod), which is a pseudo-random binary sequence with a good aperiodic autocorrelation property, for example, the Barker code, m is a sequence, Leekander and Jacobi sequences, etc. The node 4 of the control clock pulses from the output of the switch 11 is fed to the clock inputs of the correlation detector 3 and the APT 6. Signals coming from the communication channel, besides receiving them 1 binary signals by the receiver, are sampled at a pulse frequency from the clock output of the control node 4 and A11P 6 outputs in a digital code are output to a correlation detector 3. From the output of the binary signal receiver, binary information with clock pulses enters the receive cyclic distributor 2. The correlation detector 3 calculates at each the clock rate of the discretization of the correlation function of the spng-sh. h received from the communication channel with the reference signal

Q 0 5 5

0

five

0

five

0

from node 4 of the control (with a reference clock signal).

When a sync signal is detected at the output of the correlation detector 3, the maximum of the correlation function takes place, which corresponds to the receiver receiving 1 binary signals and n binary symbols of the sync code. The threshold unit 7 forms the logical value of the threshold value, which is taken as the compared value, for the time when the maximum of the correlation function is exceeded. Logical 1 from the output of the threshold unit 7 enters the correlation detector 3, the control unit 4, the controllable delay line 10, the reception cyclic distributor 2, the controlled multivibrator 8 and the front-edge pulse extraction unit 9. This logical 1 in the receive cycle distributor 2 is phased in cycles, as a result of which an information block of m bits begins to be output to the recipient of information. This logical 1 is also recorded in controllable delay line 10.

Block 9 of the leading edge of the pulse generates its short pulse on the leading edge of logical 1, which drops / counter 5 into the zero state. For the time of the presence of logical 1 at the input of the controlled multivibrator 8, the latter gives short pulses to the counting input of the counter 5, which counts them. The time of the presence of lotto 1 at the output of the threshold block 7 depends on the width of the peak of the correlation function, which is determined at the level set by the threshold. The width of the peak of the correlation function is an indirect characteristic of the quality of the communication channel, as with good signal distortion channels, they are minimal and when the clock signal is detected at the output of the correlation detector 3, there is a narrow peak of the correlation function of the maximum possible value, and for poor Channels have a washout phenomenon with a simultaneous decrease in its value} s. Consequently, the state of the counter 5 determines the quality of the gss link used.

With the back of the pulse from the output of the threshold unit 7, i.e. from the time of transition from

the logical I to the state O, the correlation detector 3 makes a reset of the previously calculated value of the correlation function, and the control unit 4 interrupts the flow of clock pulses in the ADC 6 and the correlation detector 3, thus reducing the likelihood of false phasing, since no analysis of signals in the communication channel. The state of the counter 5 determines the delay value of the logical 1 in the controlled delay line 10 and the frequency of the clock pulses at the third input of the control unit 4, i.e. which branch of the frequency grid generator 12 will be connected by the switch 1 1 to the third input of the control unit 4.

The longer the logical output of the threshold block 7, the higher the clock frequency at the third input of the control unit 4, the higher the accuracy of the calculation of the correlation function is achieved to compensate for the deterioration of the quality of the communication channel in order to increase the likelihood of a sync signal the result increases the noise immunity cicta synchronization. The longer the logical 1 is at the output of the threshold unit 7, the shorter the delay time is tuned by the counter 5, the controlled delay line 10, i.e. by a delay value smaller than the delay value of receiving t-1 binary symbols by receiver 1 of binary signals, after the fast pulse from the output of the controlled delay line 10 arrives, control unit 4, which from this moment allows the broadcast of clock pulses entering it on the third input to the correlation detector 3 and the A / D converter 6, which reduces the likelihood of false phasing due to the absence of a search for a sync signal in the information block structure with m and m bits, also due to the expansion of the sync signal search window The likelihood of detecting a sync signal is achieved by reducing the likelihood of a sync signal skipping and the structure of transmitted signals over a communication channel. L. A more correlation detector 3 begins a new search cycle cm nal i tsi

2643 G

synchronization and when detecting the maximum of the correlation function, the described process is repeated again.

The control unit 4 operates as follows.

In block 16 of the fixed memory, the model code is recorded in the digital code.

, Q (reference) clock signal, which must be detected in the communication channel. 3, the initial state at the inputs and output of the RS flip-flop 13 is the logical 0 state, the key 14 is closed.

15 The clock pulses coming from the switch 11 are fed through the key 14 to the clock inputs of the ADC 6 and the correlation detector 3 and the clock control input of the information reading unit 15. Each clock pulse from the output of the key 14, the contents of the block 16 of the permanent memory by the block 17 of information reading is supplied to the correlation detector 3. The falling edge

25 pulses from the output of the threshold unit 7, the RS flip-flop 13 is transferred to one state. Logical 1 from the output of the RS flip-flop 13 closes the key 14, thereby prohibiting the trans30 SLYATS1. ta -: tsBo x pulses from the switch P to the information reading block 5, the correlation doctr p 3 and A11P 6. The falling edge of the impulse from the output of the controlled linkage is 1C: the deceleration is performed by flip- ing the RS-trigger 1.3 restore former state 4 management and former former paf Ora.

35

Correlation detector 3 operates as follows.

Information from the output of analog-digital converter 6 is written to shift register 17, HJ of which

with each clock pulse, the information from its taps goes to multiplication unit 13, which at each clock cycle will multiply the information from the shift register 17 and the reference signal from the control 4, followed by issuing the result to the summation unit 20. In the latter, the correlation function of the signal coming from the communication channel and the reference signal stored in the control unit 4 takes place. The back edge of the pulse from the threshold block 7 resets the state of the sum 0 block. In the absence of tactical pulses, the corptation detector 3 does not work.

Controlled delay line 10 operates as follows.

A pulse (logical 1) from the output of the threshold unit 7 is recorded in the shift register 20, in which it is driven by its own clock pulses. If the control input of the switch 2 is logical O, then the switch 21 removes the last tap of the shift register 20 to the second input of the control node 4. If the state of the counter 5 is not zero, then according to the state of the counter 5, the switch 21 switches from the last tap The shift register 20 corresponds to the water oi on the agora input of the control unit 4. The maximum delay time, which determines the length of the shift register 20, is equal to the receiver receiving time 1 of binary signals t-1 of binary symbols from the communication channel.

The pulse frequency from the output of the controlled multivibrator 8 is selected on the condition that the serial i clock is output when the correlation function has the maximum possible maximum, the controlled multivibrator 8 should not have time to form the front edge of the short pulse.

Formulas

the invention

Claims (4)

one . The device is a cyclic syncro controller, which contains a switch and a carrier, but is connected to the receiver in binary mode. -la, whose chd is the input of the device, and a perimetral cyclic distributor, the input of which is an output of the oral information system, as well as a correlation speaker, to the first information inputs of which is p dmt och ° for a group of outputs of the control node, characterized by , what. in order to improve the noise-stability of the frame synchronization, a porot block, a Ukrain multivibrator, a controllable delay line, a front-to-front allocation block, a series of frequency grid generator, and an analog-to-digital converter (ADC), a co-rot: single with the input of the receiver g, ty mnh. -lots, and the LIP outputs are connected to the second information inputs of the correlation detector, to the clock input of which and the clock input of the ADC the clock output of the control unit is connected, to the first input of which, as well as to the inputs of the controlled delay line controlled by the multivibrator unit the selection of the leading edge of the pulse, the control input of the cyclic distributor and the reset input of the correlation detector are connected to the output of the threshold unit, to the input the output of the correlation detector is connected, the outputs of the controllable delay line and the switch are connected to the second and third inputs of the control unit, respectively, the control inputs of which and the control inputs of the controlled delay line are connected to the counter outputs, to the counting input and the reset input of which the outputs of the controlled multivibrator are connected and The glitch of the leading edge of the pulse 2. The device according to claim 1, about tjj and - that the control unit is made in the form of serially connected RS-tritger and key, as well as serially connected fixed memory block and block of read-rotary information, 5 clock input 0 o - the etching of which is connected to the zykhp K ... T, with the S and the E input of the RS-tilgger and the second key input being -.respectively the first, second and Tpeib inputs of the control node, -j clock output and group the outputs of which are the output of the key and the outputs of the information reading unit. 3. The device according to claim 1, about tl and - -. The first step, the correlation detector is made in the form of a state-owned JuaTenbHO connected registry server 1 ha, the multiplication unit and the summation unit, the output of which is the m correlation detector is enumerated and repeated. The info-mapping entrances of which are respectively; The second is the second VUODY of the block, multiplying the shift shear, the clock depth of which is associated with the clock input of the multiplication unit and is the clock input of the correlation detector for which the reset input is RHF, the reset input of the block is, summing. 4. The device according to claim. Characterized in that the controllable delay line is made in the form of a shift register, whose last taps are connected to the inputs of the switch, The control inputs of which are the control inputs of the controlled delay line, the input and output of which are, respectively, the input of the shift register and the output of the switch. Fiá.1 FIG. 2 f Phage. 3 one go Rig. H