SU1619398A1 - Angle-to-code converter - Google Patents

Abstract

The invention relates to analog-to-digital conversion of information, namely to converters of the angle of rotation of the shaft into a code. The aim of the invention is to improve the manufacturability of the converter. The goal is achieved by the fact that in the angle converter there is a code containing a code disk with a bit path in the form of a pseudo-random binary sequence, two; reading elements of bits set relative to each other at a distance of item x, where p is the transducer, ah is the quantum value, two elements AND, two reading elements of sampling discretization, two elements AND, two pulse drivers, four elements OR, two RS-flip-flops, two counters modulo n, reversible shift register, decoder, sample sampling track, made uniformly quantized, the quantization step is x, the bit track is made in the form of pseudo-random double gradations ary maximal length sequence with period M 2 -1, in which a number of successive n-1 zeros added zero. The read sampling elements of the samples are located at a distance of 06 x / 4 (4k + l), where k 0, 1, 2 ... According to the signals from the outputs of the reading sample discretization elements, pulses are formed which, depending on the direction of movement to the reversible shift register The information from one of the reading elements of the bits. After accumulating p quanta of information in the register, its information is fed to the output of the converter through a decoder. The construction of the code disk and the arrangement of the reading elements make it possible to increase the size of the converter without increasing the number of reading elements of the circuits. 2 Il. SS (L and with GO CO 00

Description

The invention relates to analog-to-digital conversion of information, namely, to converters of the angle of rotation of the shaft into a code.

The aim of the invention is to improve the manufacturability of the converter.

Figure 1 shows the structure of the angle-code converter; Fig.2 time diagrams of converter operation.

Angle - code converter contains code disk 1, bit track 2, sample sampling track 3, reading elements 4 and 5 of bits, reading elements 6 and 7 of sample sampling, threshold elements 8-11, elements AND 12-15, elements OR 16 -19, pulse formers 20 and 21, RS flip-flops 22 and 23, counters 24 and 25 modulo n, reversible shift register 26, decoder 27, zeroing input 28, converter outputs 29. The code disk 1 contains one bit path 2 of 2 quanta with the arrangement of binary gradations on bit 2 so that 2 code combinations of any n consecutive quanta x do not repeat along the entire length of bit 2. For example, on a bit track 2 code disk 1 marked binary code

f a- j-, 1 1, M + 1,

where the binary sequence is Ga; I is a pseudo-random sequence of maximum length with a period of M 2 -1, obtained using an n-bit shift register with modulo-two adders in a feedback circuit, in which -1 zeros added zero. Moreover, the symbols 1 of the sequence | a; i correspond to the active, and to the symbols 0m - the passive portions of the bit 2, equal in magnitude to the quantum x of the bit track 2 of the code disk 1. Track 3 of the sampling discretization is performed in steps equal to the quantum x of the bit path 2 code disk 1 (where the track pitch 3 of sampling1 samples contains equal to one active and one passive sections of track 3 sampling of samples). Track 3 sampling samples and bits of track 2 of the code disk 1 are phased relative to each other along the boundaries of quanta. The read element 6 of the sampling of the reference is shifted along the track 3 of the sampling of the samples relative to the reading element of 4 bits by an angular value of j gax, where m O, 1, 2.

The read element 4 of the sampling of the reference is shifted in the angle by the value ot

(4k + 1) in the direction of lagging in phase relative to reading element 6 of the sampling rate, kO, 1, 2 ... The reading element in 5 bits placed on bit 2 of the code disk 1 is shifted in the direction of lagging in phase to the reading element 4 bits per angular value of Cf xn, where n is the number of bits of the converter ..

In the angle-to-transducer, the angular shifts of the reading element 4 of the sampling reference relative to the reading element 6 of the reference sampling, as well as the reading element of the 5 bits relative to the reading element of the 4 bits are made to the side of the phase by the angular values (and (o, respectively, which should be understood as shifts of the reading elements 5 and 4 relative to the reading elements 4 and 6 along tracks 2 and 3 of the code disk 1 in the same direction, for example, counterclockwise, subject to increasing the code on the bit track 2 of the code disk 1 in the clockwise direction; shifting the read sample element 6 along the track 3 of the sample clock relative to the read item 4 bits by the angular value j is independent of the received code increment.

Methods for obtaining pseudo-random binary sequences of maximum length (TPSMD) with a period of M 2P -1 are known. For example, a method for obtaining PDDM using a shift register with modulo-two adders in a feedback circuit is suitable for generating sequences with a period M to -. Sequence Ја; i

 1, M + 1 is also a PDDM with a period of M 2M-1, in which zero is added to the number of consecutively located (n-1) zeros.

Consider an angle converter - a code executed by a three-bit ().

To obtain a pseudo-random binary sequence of maximum length (SSDMT) with a period of M 2 -1 7, a primitive polynomial h (x) of third degree is necessary. Choose the polynomial h (x) x + jc + l. Upon receipt of the appropriate PDSMA, it is necessary to use a three-digit shear

5 16

The register with g is mmp 1orom modulo two in the reverse circuit, where the nature of feedback is determined by the polynomial h (x). In this example, a three-bit shift register generates PSDTTMD with a period M,. ..0010111. . . Next, we obtain the sequence a; where i 1,8. To do this, we add zero to the two consecutive zeroes (since in this case p-1) PSDPMD. Thus, the sequence takes the form Ја | 00010111. The sequence fa.Z determines the number of quanta of the bittrack 2 of the code disk 1, which in this example is eight. From 360 ° ..a

yes quantum size x 45.

about

Determine the angular value of C, to which the reading element 5 bits should be displaced along the discharge track 2 relative to the reading element 4 bits. In the example, C h.p 135 °. Thus, the reading element of the 5 bits should be shifted along the bit path, 2 counterclockwise relative to the reading element of the 4 bits at an angle of 135. Now consider the construction of track 3 sampling samples. The track spacing 3 of the sampling of the samples must be made equal in magnitude to the quantum x 45 ° of the discharging track 2 and contain equal in size to one active and one passive segments.

Angle converter - the code works as follows.

Consider first the operation of the sampling sampling path, which includes track 3 of sampling, reading the elements 6 and 7 of the sampling, threshold elements 10 and 11, shapers 20 and 21 pulses, and elements 14 and 15.

When the code disc 1 rotates, the reading elements 6 and 7 of the sampling rate can be both above the active (shaded in figure 1) and passive (not shaded in figure 1) portions of the sampling track 3. When finding the reading elements 6 and 7, the sampling of the sample over the active parts of the track 3, the sampling of the samples from the threshold elements 10 and 11 is removed, and when the reading elements 6 and 7 are found, the sampling rate

93986

Counting over the passive sections of track 3 sampling of samples is low voltage potential (Fig. 2a, e). In this case, the formers 20 and 21 of pulses give out pulses at their outputs at the moments of arrival from the threshold element 10 of the rear and leading edges of the signal, respectively (Fig. 26,

JQ c, d, d) and correspond to the rotation of the code disk 1 both clockwise (Lig. 2c, d) and counterclockwise (Fig. 26, d). When rotating the code disk 1 against the clock

5 arrows, the signal from the threshold element 11 (FIG. 26, e) permits the passage of pulses from the driver 20 pulses through the AND 15 element (FIG. 2G), and with the enemy code disc 1 along

20

clockwise signal from the threshold

element 11 (Fig.2d, e) allows the passage of pulses from the imaging unit 21 pulses through the element 14 (Fig.2z). Thus, the pulses from the outputs of the And elements 14 and 15 are removed at the moments of passage of the reading elements 4 and 5 of the bits of the centers of the quanta x of the bit 2 of the code disk 1. Consider the operation of the converter

angle - the code as a whole. Before the converter starts operation, the pulse from the input 28 is set to the zero connection trigger 23 and, through the SLI elements 17 and 18, the counters 24 and 25 are modulo (

When the code disk 1 rotates counter-clockwise from the output of an element, And 15 starts to arrive at the counting input of counter 25 modulop, through the OR 18 element at the input of setting the counter 24 modulo n into the zero state, through the OR 16 element - to the clock input of the n-bit reverse shift register 26 and to the R input of the trigger 22. The first pulse from the output of the element 15 And the trigger 22 is set to one, and the signal corresponding to the high level of voltage begins to arrive from its direct output on

one input of the element 12 and one of the control inputs of the n-bit reverse shift register 26, the second control input of which receives a low level signal from the inverse

trigger output 22. At the same time, while rotating the code disc 1 counterclockwise, the signals taken by the read element 4 bits from bit 2 in the form of a high

7 16

the voltage corresponding to the active areas of the discharge track 2, and the low-voltage level corresponding to the passive sections of the discharge track 2, through the threshold element 8 begin to flow to another input of the element 12 and further through the element 12 to the information input of the p-discharge one reversible shift register 26. By pulses that are fed to the clock input of the n-bit reversing shift register 26 from the output of the element OR 16, information signals arriving at the direct input of the n-bit reversing shift register Page 26, start sequentially from right to left to fill the memory cells of the n-bit reverse shift register 26. After the n-th pulse arrives from the output of the element 15 on the counting input of the counter 15 modulo n on its output, an impulse appears which the OR 19 element sets the trigger 23 to the single state, and the signal corresponding to the high voltage level, from its direct output, begins to flow to the control input of the decoder 27, after which the information signals about the angles can be taken from the decoder 27 th position of the code disk 1. After the n-th pulse arrives at the clock input of the n-bit reversible shift register 26, it records information from the units and slugs corresponding to the active and passive parts of the bit track 2, and the code disk 1 is rotated by the angular value (x . With further rotation of the code disk 1 counterclockwise, each successive impulse arriving at the clock input of the n-bit reversible shift register 26 shifts its contents by one bit to the left while simultaneously compiling information signals to the direct input of the n-bit reversible shift register 26 in the form of a high or low voltage level, which correspond to the active or passive parts of the bit-track 2. When the n-bit reversing shift register 26 is input to the clock input Starting from the nth, 2 different states are successively fixed in it, which corresponds to a complete

0

five

3988

the code disk 1 rotation. The decoder 27, after receiving a high level signal from its forward-enabling input from the forward output of the trigger 23, converts 2 different code combinations of the n-bit reversing shift register 26 into the output n-bit code, for example, an ordinary binary code. The decoder 27 also sequentially with the arrival of clock pulses on the n-bit reversible shift register 26 converts the code combinations of the register 26 into the output code of the converter.

In the case of a three-bit angle-code converter (see linear scan of the code disk in Fig. 1), after the third cycle of operation, while rotating the code disk 1 counterclockwise, the information from the three low-level signals is recorded in the form of a three-bit reversing shift register 26 With further rotation of the code disk 1 in the same direction, the signals in the form of code combinations 001, 010, 101, 011, 111, ON, 100, 000, 001 ... are sequentially fixed in the three-bit reversible shift register 26. If, as a decoder 27 in the device e is used read only memory (ROM), the codewords corresponding to 2L razlich0

five

0

five

0

five

0

five

The n-bit reversible shift register 26 states will be the addresses for the ROM on which codes (for example, a regular binary code) corresponding to different angular positions of the code disk 1 will be written in it. For a three-bit angle converter - the code and the conversion of 1 of the shaft rotation angle into the ordinary binary status code of the three-bit reverse shift register 26-000 correspond to the information recorded in the ROM-000, the state 001-001, 010-010, 101-011, 011-100, 111- 101, 110-110, 100-111.

When the code disk is rotated clockwise, the pulses from the output of the And 14 element begin to flow to the counting input of counter 24 modulo n, through the OR 17 element to the input of setting the zero state of the counter 25 modulo n, and through the OR 16 element to the clock the input n-bit reversible shift register 26 and the R input of the trigger 22.

ten

15

25

The first pulse from the output of the element 14 and the trigger 22 is set to the zero state and the signal corresponding to the high voltage level from its inverse output begins to flow to the second input of the element 13 and the second control input of the regular reverse shift register 26 to the first the control input of which receives a low voltage signal from the direct output of flip-flop 22. Simultaneously during the rotation of the code disk 1 in the clockwise direction, the signals taken by the reading element 5 from bit 2 are in the form of high voltage level corresponding to the active portions of the discharge track 2, and a low level voltage corresponding passive lan - ,,. cam bit track 2, through the threshold element 9 begins to arrive at the first input of the element And 13 and then through the element And 13 to the reversing input of the n-bit reversible shift register 26. By impulses that are fed to the clock input of the n-bit reversing shift register 26 from the output of the element OR 16 information signals arriving at the reversing input of register 26, begin sequentially from left to right to fill the memory cells of the n-bit reversing shift register 26, After the nth pulse from the output of the element This AND 14 at the counting input of the counter 24 by the module and at its output appears a pulse, which through the element OR 19 sets the trigger 23 to the one state and the signal corresponding to the high voltage level, from its direct output starts to flow to the enable input of the decoder 27, after which the decoder 27 can be used to remove information signals about the angular position of the code disk 1. After the n-bit reversing shift register 26 of the n-th pulse arrives at the clock input, the information consisting of Hive and units corresponding to the active and passive portions of the discharge track 2, wherein the code disk 1 is rotated at an angular value a. With further rotation of the code disk 1 in the direction of the hour hand each successive impulse arriving at the clock input of the n-bit reversing shift

thirty

40

45

50

55

ten

 ,

9398 | °

register 26, shifts its contents by one bit to the right with simultaneous arrival of new information signals at the n-bit reversing input of the reversing shift register 26 in the form of a high or low voltage level, which corresponds to the active or passive part of the bit track 2. When entering the clock input p15

25

 ,,.

thirty

40

45

50

55

the bit reversible shift register is 26 2 clock cycles, beginning with the nth one, 2 different states are successively fixed in it, which corresponds to the complete rotation of the code disk 1.

Consider the reverse mode of the converter angle - code.

When the code disc 1 rotates by an angular value. -N clockwise or counterclockwise, the trigger 23 is set to one and the signal corresponding to a high voltage level from its direct output goes to the enable input of the decoder 27, and The n-bit reversible shift register 26 contains information about the angular position of the code disk 1. When the direction of rotation of the code disk 1 is changed, the first pulse from the output of the AND 14 or 15 element switches the trigger 22. At this signal you A high voltage level from its direct or inverse output is connected to the forward or reverse input of the n-bit of the dy shift register 26 of the read element 4 or 5 bits, respectively. The signals from the forward and inverse outputs of the trigger 22 serve to organize the reverse mode of the n-bit reverse shift register 26. Thus, in the angle-to-converter, the first (n-1) clock cycles (quanta x) are preparatory, after which any of the above modes of operation of the converter.

Claims (1)

Invention Formula Angle converter is a code containing a code disk with a bittrack made in the form of gradations of a pseudo-random binary sequence, the first and second reading elements of bits located opposite the bittrack and set relative to each other at a distance n, where n is bit converter size, ax is the quantum of the converter, two elements characterized in that, in order to improve the manufacturability of the converter, two reading elements of the sampling rate, two elements And, two are entered into it pulse maker, four OR elements, two RS flip-flops, two modulo n counters, reversible shift register, decoder, code disk is equipped with a sample sampling track, made evenly quantized with a quantization period, the bit width is made in the form of pseudo-random binary sequence gradations lengths with a period of M - 2 -1, in which zero is added to the number of consecutive n-1 zeros, the first and second reading elements of the sampling are set against the track iskretizatsii samples spaced about X  t (4k + 1) from each other, where k 0 five 0 five  inputs of the third and fourth elements And, respectively, the output of the second sampling readout element is connected to the second inputs of the third and fourth elements And, the output of the third element And is connected to the S input of the first RS flip-flop, the first inputs of the first and second elements OR, and the counting input of the first counter modulo p, the output of which is connected to the first input of the third OR element, the output of which is connected to the S input of the second RS flip-flop, the output of which is connected to the control input of the decoder, the outputs of which are the converter outputs, the output of the fourth element AND is connected to the R-inputs of the first RS flip-flop, the second input of the first OR element, the counting input of the second modulo counter and the first input of the fourth OR element, the output of which is connected to the converting input of the first module modulo p, the zeroing input of the converter is connected to the R input of the second RS flip-flop, the second input of the fourth OR element, and the second input of the second OR element, the output of which is connected 0,1,2 ..., and the first reading element, 0 with the zero input of the second counter The sampling time of samples is located relative to the first reading element of the bits at a distance of j mx, where m 0,1,2 ..., the outputs of the first and second reading elements of the bits are connected to the first inputs of the first and second elements, respectively, whose outputs are connected respectively with the first and second information inputs of the reverse shift register, the output of the first sampling readout element is connected to the inputs of the first and second pulse formers, the outputs of which are connected to the first modulo p, the output of which is connected to the second input of the third element OR, the direct output of the first RS flip-flop is connected to the second input of the first AND element and the first control input of the reverse shift register, the inverse output of the first RS-flip-flop and the second control input of the reverse shift register, the outputs of which are connected to the information inputs of the decoder, the output of the first OR element is connected to the clock input of the reverse shift register. one T K | H 0 xh Xh-j / one I 3 iS V4 "CV CT T CVI vi ABOUT I "Vj B L ate