SU1619259A1 - Device for converting coordinates - Google Patents

Abstract

The invention relates to computing and can be used in specialized computers when converting coordinates. The aim of the invention is to improve the speed of performance by organizing a conveyor conversion mode. The device contains n conversion units (PSUs) (n is the number of intervals for splitting the angle code), each of which contains registers 1 abscissa and 2 ordinates register 3 angles, block 4 of memory of conversion constants, adder 5 abscissas, adder 6 ordinates, registers-shifters abscissas 7 and ordinates 8, control block 9. 1 il.

Description

The invention relates to computing technology and can be used in specialized processors for coordinate conversions in control systems for robots and manipulators, as well as in navigation, guidance, etc.

The aim of the invention is to improve performance by organizing a conveyor mode of the conversion. Niya.

The drawing shows a functional diagram of the device.

The device contains η transformation blocks (BP), η is the number of angle code partition intervals, each of which contains abscissas register 1, ordinates register 2, angles register 3, transform constants memory block 4, 5 ”abscissas adder, 6 ordinates adder, register abscissa shifter 7, ordinate shifter 8, ordinate 8, control unit 9, containing first 10, second 11, third 12, fourth 13 triggers, first 14, second 15, third 16, fourth 17 OR elements, first 18 and second 19 ele-, cops And, first 20 and second 21 counters, decoder 22 ..

Each conversion unit also contains an input of 23 abscissas, an input of 24 ordinates, an input of 25 angles, an output of 26 abscissas, an output of 27 ordinates, a synchronizing input 28 of the angle register, a synchronizing input 29 of the control unit, an input 30 of the initial installation, input 31. start, exit 32 of the end of the calculation, the generator 33.

The determination of the result of the coordinate transformation is carried out in accordance with known expressions

X ^r = X · cos cp - Y <sin Cp, Y ^z = Y-cosCf + X-sincp,, If the coordinate codes X and Υ are broken? on M equal in bit depth parts, a ^; if the angle code is N parts, then the initial data will be written in the form ^{+ X} M ".5 (ί).

X = X, + x ₄ + ...

Y = Y <+ Y ₂ + ... +

Cp = (Pi + Cp + ··. +

Substituting expressions (2) into expression (1) and after a series of transformations, we can come to the re-relation relations by which this device operates

X ¹

Y ^j

Μ-ι

M ~ 1

-’P where

Xbd. · 2-P <= 0 M-ι | ² ,> o

are the conversion constants.

The device operates as follows.

Initially, the entire device is Ί set to the initial position, registers 1 and 2 are set to the Record position ”, then the coordinates X and Y are entered into these registers, the angle code φ is written into the angle register 3, the signal” Start ”is sent to trigger 12 at input 31 . By setting the trigger 12 to one, the pulses from the generator 33 are allowed to pass through the And element 18 to the counter 20, the signals from the output of which are sent to the decoder 22. The pulse from the first output of the decoder 22 sets the trigger 11 to the position for enabling the reading of constants from the memory unit 4. The pulse from the second output of the decoder 22 is set by the trigger 13 in the installation position of the registers. shifters 7.8 per record. The pulse from the third output of the decoder 22 resets the trigger 11, simultaneously passing through the OR element 15 to the sync input of the shift registers 7 and 8. The pulse from the fourth output of the decoder 22 sets the triggers 10 and 13 to the shift position by P bits -: registers 1 and 2 registers -shifters 7 and 8. The following R. pulses of the decoder 22 through the elements OR 16 and 15 produce a shift of the data in the shift registers 7 and 8, and then. cut elements OR 16 and 14 - shift in registers 1 and 2, the Next pulse of the decoder 22 increases the counter 21 by one. Counter 21 counts the number of converted bits of the X and координат coordinates. If the coordinates are completely transformed, at the output of counter 21 there are signals that 5Ф arrive at element And 19, from the output of which the signal goes to output 32 of the unit, simultaneously resetting: counter 20 and trigger 12. The last one ^is '. The decoder pulse 22 resets the count, chick 20 through the OR element 17. After the end of the coordinate transformation in the ί-th block, the resulting coordinates obtained in this block appear at the outputs 26 and 27. To registers

1-3 you can enter new information. Thus, a fan-like method of converting the dinates is obtained.

concourse—

Claims (1)

Claim A device for converting coordinates containing an abscissa register, an ordinate register, an angle register, a memory block of conversion constants, an abscissa adder, an ordinate adder and a control unit, the abscissas and ordinates of the device being connected to the information inputs of the abscissa, ordinate and angle registers, respectively And moreover, in order to improve performance by organizing the conveyor mode of conversion, p-1 abscissa registers are additionally introduced into it (n is the number of intervals for splitting the angle code), -1 ordinate registers, n-1 angle registers, n-1 memory blocks: conversion constants, η-1 abscissa adders, n-1 ordinate adders, n-1 control blocks and n shift registers, abscissas and ordinates, and outputs, j-ro of the abscissa register, j-ro of the ordinate register and j-ro of the angle register (j = "1, ..., p) are connected by the address input j-ro of the memory block of the conversion constants, the first and second outputs of which are connected to the inputs of the first terms jx adders abscissa and ordinate, respectively, the outputs of which are connected to the information inputs jx registers-sd igateley abscissa ordinate th respectively, the outputs of which are connected to the inputs vto10 1619259 6 terms of jx adders abscissa and ordinate, respectively, outputs ix of shift registers of abscissa and ordinate (i = 1, ..., n-1) are connected to information inputs (i + l) -x of register of abscissa and ordinate, respectively ₉ outputs η registers of motors are connected to the outputs of the abscissa and ordinate of the result of the device, respectively, information. The inputs of the angle register from the second to the nth are connected to the inputs of the angle of the device, the start and synchronization inputs of the first control unit are connected to the inputs of the device of the same name, the first output of the j-ro block the board is connected to the inputs of the jth abscissa and ordinate registers, the second output j-ro of the control unit is connected to the synchronizing inputs jx of the abscissa and ordinate registers, the third output of the control unit is connected to the j-sample enable input of the memory block conversion constants, the fourth output of the j-ro control unit is connected to the inputs of the jx mode of abscissa and ordinate shift registers, the fifth output of the j-ro control unit is connected to the synchronization input of jx abscissa-shift registers: cissuses and ordinate, the output of the end of calculation i-ro of the control unit is connected to the start input and the synchronizing input (i + l) -ro of the control unit, the initial installation input of all control units is connected to the device input of the same name, the synchronization input j-ro of the angle register is connected to the input of the same name.j -ro control unit.