SU1619251A1 - Series adder in redundant binary computation system - Google Patents

Abstract

The invention relates to computing and can be used in computing devices operating in a redundant binary number system. The aim of the invention is to improve the accuracy. The adder contains a negative sum generation unit 3, a positive sum generation unit 14, a positive transfer formation unit 11, a result generation unit 15, an OR-NOT element 7, a delay element 4,8,16. 2 ill., 2 tab.

Description

§

V

FIG.

The invention relates to computing and can be used in computing devices operating in a redundant binary number system.

The aim of the invention is to improve the accuracy.

FIG. 1 shows a block diagram of the adder; in fig. 2 - functional block diagram of the formation of the result.

The adder contains inputs 1 and 2, to which the direct (or inverse) values of the modules of the first and second operands a, b (a, b) s are fed into the negative sum-sum block 3, the delay element 4, the inputs 5 and 6, to which the inverse is fed the negative values of the operands (a, b), the element OR-NOT 7, the delay element 8, the inputs 9 and 10, to which the negative values of the operands (a, tT), the positive transfer formation unit 11, the inputs 12 and 13, are applied which are given the inverse values of the modules (or inverse positive values) of the operands a, b (), block 14 forms a positive sum, a result setting unit 15, a delay element 16, outputs 17 and 18. Block 15 (FIG. 2) contains an element 2I-ZILI-NOT 19, an element NOT 20 and OR-NOT 21, an element 2I-ZILE-NOT 22 Block 3 contains the element EQUALITY 23. Block 14 contains the element EQUITY 24. Block 11 contains the element 2 – ZILE – NE 25.

The algorithm of the adder has

following view:

(1 at O at 2; -1 at C, -2, where, +1/2 (a1 + g + b; + g);

i -1,0, ..., N; Z0 - overflow discharge.

4.8 and 16 delay elements are the storage register of the ostak from the previous summation cycle of the operands.

Qr2 (; - "+ a Chg + Ng) -421- The value of the residue depending on

The code in the delay elements is as follows: q. – 2 as,,

f -1priS Z 0, 1,

Q.0priS, 0,

 or S - 1, S 0,

Q; 1 when S 0,, S + 1;

Q; 2 when S 0, S 0, S 1.

To clarify the operation of the adder, Table 1 shows the possible states of the adder.

The device works as follows.

Input operands are fed to the inputs 1,2,5,6,9,10,12,13 in sequential code, high-order bits.

The element EXCLUSIVE OR 23 forms the value of the first negative sum

I

, 42V5; 42b) W.

The element OR NOT 7 forms the value of the second negative sum (equality of the sum of the operands -2)

„-2

I-1

a, 42bUz

The logical expression for the positive transfer driver (block 11) is

p, h, amb nva7 «/ b7 + z

or

p +

HI

a 4ibr "Vai4zvbi4Z

The element EXCLUSIVE OR 24 forms the value of a positive sum

st pt V hT1

;-them

Logical expressions for the result are

 P. +, i it (i + i t-H h

35

,,

In tab. Figure 2 shows an example of adding AdO.TIO numbers and, 1010 in the device (,, That).

Claims (1)

Invention Formula A sequential adder in an excess binary number system containing blocks for generating positive and negative sums, a block for forming a result, and two delay elements, the inputs of the block for forming a negative sum are connected to the first and second inputs of the adder, and the output which is connected to the first input of a positive sum generating unit, the output of which is connected to the input of the second delay element, the direct and inverse outputs of which are connected respectively tween the first and second inputs of the block for516192516 result, the outputs of which the delay element and the output are interlocked with the corresponding output of the formation of a positive resummator, with this unit Normalization of the nose, and the unit of forming the negative sum contains the element of the result contains two elements 2I- EXCLUSIVE OR, the inputs and output of which -ZIL-NOT, the element NOT and the element OR-NOT, are connected respectively to the input-inputs of which are connected to the third and to the output of the specified block, to the block inputs of the block, to the inputs of the first formation of the negative c The mms of the co-group of the first element 2И-ЗИЛИ-NOT hold the element EXCLUSIVE OR, the inputs are connected to the output of the element NOT and p - and the output of which is connected by the corresponding input of the block, the input of the second group is connected to the first input of the block unit, the first and second inputs of the sum of the third group - the values of the modules (or in-ka, and the output connected to the first output are the absolute values of the modules) of the first and | the block, the inputs of the first group of the second second operands of the adder, on the trans-element 2I-ZILI-NOT are connected to the fourth and fourth outputs of the adder to the inverted and the sixth inputs of the block, the positive and negative elements of the second group are connected to the output elec- value of the result of the adder, ment OR-NOT, the input of the third group characterized in that, 20 is connected to the first input of the block, and in order to improve accuracy, the totalizer input is connected to the second output of the block, contains the third delay element, the ele-input of the element is NOT connected to sixth kent or not block forming polo block inlet. careful transfer, the inputs of which are Table 1 from the first to the fourth are connected respectively to the inputs of the third to the sixth, to which the inverse values of modules (or in - 2-2-5-2-1 positive values) and from - 2-1 4.5 -1 -1 Valid values of the first and second are 30 20-40-1 th operands of the adder, and the output under - 2 + 1 3.5 +1 -1 keys to the second input of the block formiro - 2 + 2-3 + 2 -1 Vani positive amount, with this, 1-2-30-1 positive ne formation unit - 1-1 2.5 +1 -1 Renos contains element 2И-ЗИЛИ-НЕ, ,, - 10-2 + 2-1 the inputs of the first group of which are connected - 1 + 1 1 5 -1О with the first and second inputs of the block, -1 + 2-100 the input of the second group is connected to the third 0-2-1-2O block input, the input of the third group is co-0-1-1 / 2 -1O united with the fourth block input, and to the output is connected to the output of the block, inputs 0 + 1 + 1/2 + 1O the element OR is NOT connected to the seventh 0 + 2 + 1 + 20 and the eighth inputs of the adder, on which is + 1-2-I00 inverse negative inverse - + 1 1 + 1.1 / 2 + 1О values of the first and second operands adder, and the output is connected to the input + 1 + 1 + 2.5 -1 + 1 the third delay element, forward and + 1 + 2 + 30 + 1 inverse outputs of which are connected + 2-2 + 3-2 +1 respectively with the third and fourth + 1 + 3.5 -1 +1 the inputs of the formation unit the one, fifth and sixth inputs of which are + + + 4.5 + 1 + 1 are united respectively with the output of the per- + i + 5 + 2 +1 . ± l iti ± 2i jiJLiL Table . ± l iti ± 2i jiJLiL Table 2 ## d.2