SU1617621A1 - Device for shaping linearly frequency-modulated signals - Google Patents

Abstract

The invention relates to radio engineering and can be used in radio transmitting and receiving devices for generating linear frequency-modulated (chirp) signals with rapidly changing parameters. The purpose of the invention is to expand the frequency range of the generated signals. The device for forming the chirp signals contains the first accumulating adder 1, the combinational adder 2, the second accumulating adder 3, the first memory block 4, the digital-to-analog converter 5, the switch 6, the switch 7, the filter block 8, the frequency divider 9 by M, the second memory block 10 TI, counter 11, generator 12 start pulses, generator 13 pulses, frequency divider 14 with a variable division factor. The goal is achieved by changing the division ratio of frequency divider 14 and, consequently, the switching frequency of switch 6 in the device in accordance with the varying control code. As a result, the position of the main frequency component of the signal spectrum at the output of switch 6 changes It is not possible to change the carrier frequency of the chirp signal generated at the output from F _n to F _n + MF _t . 2 Il.

Description

at

in S.

/ g

//

/ 2

FIG.

f

The invention relates to radio engineering and can be used in radio transmitting and receiving devices for generating linear frequency-modulated (chirp) signals with rapidly changing parameters.

The purpose of the invention is to expand the frequency range of the generated signals.

Figure 1 shows a structural electrical circuit of a device for generating chirp signals; 2 shows diagrams for his work.

 The chirp signal shaping device includes a first accumulating adder 1, a combinational adder 2, a second accumulating adder 3, a first memory block 4, a digital-to-analog converter (DAC) 5, a switch 6, a switch 7, a filter block 8, a frequency divider 9, a second block 10 memories, a counter 11, a start pulse generator 12, a pulse generator 13 and a frequency divider 14 with a variable division factor.

The device for the formation of chirp signals operates as follows.

The trigger pulse generator 12 generates trigger pulses, the frequency of which corresponds to the frequency of the generated chirp signals. The positive (single) trigger pulse level is used as a signal to zero the first and second accumulating adders 1 and 3. The negative (zero) level of these pulses is a signal that permits the operation of the pulse generator 13, which, within the negative trigger pulse, forms a packet of frequency pulses fr Mf which, after dividing by M in frequency divider 9, are used as synchronization clocks of accumulating adders 1 and 3. Positive differences in trigger pulses change the state of the counter and 11, which counts their number. The output code of the counter 11 is an address code, upon receipt of which the modulation rate code K is read from it to the input of the second memory block 10 to the input of the first accumulating adder 1. to the input of the combinational adder 2 - the code of the initial frequency Kf, to the divider 14 of the frequency with a variable division factor - the code of the division factor Kd and to the input of the switch 7 - the code of the connected filter Kf. The second memory TO block consists of four matrix-type memory devices, which are polled with the same Address Code. Each of the four storage devices contains 5

There is a set of values for one of the four indicated Kpl codes,. KfH, cd. Kf. Thus, the second memory block 10 is a device for storing the program for changing the parameters of the generated chirp signal from pulse to pulse. The memory capacity of the second memory block 10 and the width of the counter 11 determine the number of possible choices of the carrier frequency and frequency deviation of the generated chirp signal, which varies in each period of the trigger pulses in accordance with the order in which they are pre-recorded in the second memory block codes K p ,,, Cgn. Cd and Kf. When forming the next negative (zero) potential of the start pulse, the generator of 13 pulses starts to generate. Impulses from its output with. frequency fr Mg5; They are fed to a frequency divider 9, in which the pulse frequency decreases by a factor of M. The resulting clock pulses of the frequency ft synchronize the operation of accumulating 1x adders 1 and 3. The output code of the first accumulating adder 1 increases with the arrival of each clock pulse by the value of K p, which results in an approximation of the linear law of the chirms signal frequency. In the combination adder 2, the code of the initial frequency Cn is added to this code. The codes for the current chirp signal frequency generated in this way are summed and

5 are accumulated in the second accumulating adder 3. The result of accumulating linearly varying codes, which corresponds to digital integration, is quadraticly variable

Q is the output code of the second accumulating adder 3. Thus, the discrete values of the quadratic phase variation law of the chirp signal are calculated. The phase codes of the output of the second accumulating bag 5 of the mat 3 are used as address codes for accessing the first memory block 4. In the first block 4, the memory is digitally recorded the counts of the chirp signal in the rows, the addresses of which correspond to 0 phase counts from the second accumulating adder 3. The output of the first memory block 4 is received with a clock frequency fi discrete values of the chirp signal in digital form . D / A converts 5

5 chirp signal to analog form. At the first output of the DAC 5, the signal has the form of a sequence of square-wave pulses with a frequency fr, the amplitudes of which correspond to selective values of the chirp signal at the instants of the onset of pulses.

0

five

0

This signal is represented in Figure 2a by a bold line. Such a signal can be recorded in video

ST (t) IS (ICr) / Uo (t-r) f7 (r-KT Xk. (1)

k 0 °°

where Vo (t) is a rectangular pulse of duration T; T 1 / fi;

d (t) is the delta function;

S (KT) -value of the non-discriminatory chirp signal at times tK K -T.

Unsampled chirp signal

(2)

has the appearance

S (t) Uo cos 2l (fHt + 0.5 / 3 t).

The signal spectrum (1) has the form

("-N} (3)

where S (W is the chirp signal spectrum (2).

The signal at the second output of the D / A converter 5 is inverse: and t (t) -Ur (t).

The divider 14, depending on the control code Cd from the second memory block 10, divides the pulse frequency fr by P 1 ... M times. The frequency pulses TD fr / P thus obtained control the operation of switch 6, which, with positive pulses, passes the signal from the first output of the DAC 5 to the output, and from the second output to the negative. As a result, a periodic pulse signal of frequency fd 1 / To is formed at the output of switch 6. modulated by a discrete chirp signal (1) (FIG. 2a). This signal is a discrete analogue of the signal at the output of a balanced modulator with modulation of the harmonic signal fd by the chirp signal (Fig. 26). As a result, it is ensured that the signal spectrum at

the output of switch 6, in contrast to the spectrum of the signal at its input, is transferred to the higher frequency side by the value of fd. Since the signal at the output of switch 6 is discrete, its spectrum is also discrete in frequency. The restoration of a continuous signal from a discrete signal is performed by isolating the main spectral component with a bandpass filter. In the device, in accordance with the variable control code, the division factor of the frequency divider 14 with a variable division factor changes, and consequently, the switching frequency fd of the switch 6. As a result, the position on the frequency axis to be extracted is changed. the signal at the output of the switch 6. This allows the program to change the carrier frequency of the signal from fH to Hn +

Mfi, but it is necessary to change the center frequency of the passband of the recovery filter. For this purpose, the bandpass filters included in the filter unit 8 have center frequencies f +

ltdgde 1 1.2M number of the filter. To exit

Switch 6 in each chirp signal shaping cycle is connected to a filter, the P number of which coincides with the division factor of the frequency divider 14 with a variable division factor in this cycle. Thus, at the output of filter unit 8 and the entire device, there is a chirp signal, the carrier frequency of which varies from period to period of program triggers in the frequency range from fh to Mfr with a step fi. In addition, at each of the division factors of the frequency divider 14 with a variable division factor, the carrier frequency of the chirp signal may change with less discreteness by changing the code of the initial frequency Kg. The magnitude of the frequency deviation of the chirp signal Afc may also change during each generation cycle by changing the modulation rate code Kp ,.

Claims (1)

Invention Formula A linear frequency modulated signal shaping device comprising a first accumulating adder, a combination adder, a second accumulating adder, a first memory block and a digital-analog converter, as well as a pulse generator and a filter unit, in series with the aim of expanding the range of frequencies generated signals, a frequency divider, a switch, a frequency divider with a variable division factor, a switch and a series-connected pulse generator are introduced ska, the counter and the second memory block, the first and second outputs of which are connected to the input of the first accumulating adder and the second input of the combinational adder, and the third and fourth output of the second memory block are connected to the control inputs of a frequency divider with a variable division factor and a switch The outputs of which are connected to the inputs of the filter unit, the output of which is the output of the device. the output of the start pulse generator is connected to the control input of the pulse generator and the zeroing inputs of the first and second accumulating adders, to the synchronization inputs of which the output of the frequency divider is connected, to the input of which and the input of the frequency divider with shifting variable division factor alternating division factor is connected to the first one, respectively, the output of the pulse generator is accurate, with the third and third inputs of the switch, the first and second outputs of the digital-analogue input of which is connected to the input the converter and the output of the frequency divider 5 switch. sa) but Thebes. 2