SU1615751A1 - Integration device - Google Patents

Abstract

The invention relates to computing and can be used in measurement technology and in automation devices. The aim of the invention is to improve the accuracy and increase the integration time. The device contains an integrator with zeroing 1, a pulse generator 2, a delay element 3, a storage unit 4, a comparator 5, pulse counters 6, 7, a shaper 12 reset pulses, a digital-to-analog converter 9, a threshold unit 10, a key 11, an integrated time setting device 8. Range the input integrable signal and the integration time can be large and are limited only by the number of bits in the counter 7 and in the storage unit 4. 1 Cp. files, 3 sludge.

Description

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The invention relates to computing and can be used in measurement technology and automation devices.

The purpose of the invention is to improve the accuracy and increase the integration time.

Figure 1 shows the functional diagram of the device; FIG. 2 is a diagram of a reset pulse shaper, an option; on flash-.3 - the diagram of the integrated device operation.

The device (Fig. 1) contains an integrator 1 with zeroing, a generator of 2 pulses, a delay element 3, a storage unit 4, a comparator 5, the first 6 and second 7 counters, a setting unit 8 g of integration time, a digital-analog converter (D / A) 9, a threshold block 10, the key 11 and the driver 12 pulse reset. The shaper 12 reset pulses | contains the elements OR 13, AND 1D and | OR 15, the waiting generator 16 pulses | element AND 17 (FIG. 1), as well as the comparators 18 and 19, the elements 20 and OR | 21 and waiting generator 22 pulses I (figure 2).

The device works as follows.

When a signal appears at the output of the setpoint 8 for the integration of the signal, the duration of which corresponds to the integration time interval (Fig. 3a), the device begins to integrate the input signal (Fig. 3c). The signal from setpoint 8 opens; key 11 and removes the zero-setting command from the second counter 7 at the output of integrator 1 with zeroing. The voltage increases (FIG. 3g).

The voltage at the first input of the comparator 5 begins to exceed the voltage at the second input of the comparator 5, which is equal to zero before the next integration. At the output of comparator 5, a signal appears giving permission to the first 6 and second 7 counters to receive pulses from the generator of 2 pulses. Counters 6 and 7 begin to simultaneously receive input pulses. The output code of the counter 6 is fed to the ASL 9. The voltage at the output of the D / A converter 9 begins to increase (Fig.ZD).

At the moment of equality of the analog signal from the DAC 9 and the variable voltage of the integrator 1, a signal appears at the output of the comparator 5

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The pulses are counted by counters 6 and 7. The output voltage at the DAC 9 stops increasing, and continues to increase at the output of integrator 1, as a result of which the comparator outputs a signal that counters 6 and 7 receive from the generator 2 pulses.

The voltage at the output of the DAC will increase. Thus, the output voltage of the DAC monitors the voltage at the output of the integrator 1 (Fig. 3g, d), and counters 6 and 7 record the number of pulses corresponding to the voltage at the output of the integrator 1. For this variant of building the reset pulse generator 12 (Fig. 1), certain bits per element OR of the former 12 are determined from the first counter of 6 pulses, which determine the range of numbers recorded in counter 6, in which the output of the element OR 13 The signal arriving at the first input of the element is And 14. The duration of this signal is determined by the time interval during which the number in the counter 6 in the specified range varies from the minimum to the maximum value. If in this time interval the input integrable signal is reduced to zero or to some predetermined value determined by the reference voltage in the threshold unit 10, then the threshold unit 10 generates a signal (Fig. ZJ) which is fed to the element And 14 of the former 12, as a result of which, at the output of the AND 14 element, a signal arrives through the OR 15 element to the waiting generator 16 of pulses. The shaper 12 generates a short pulse with a duration sufficient for setting zero (discharge of the integrator's capacity) of integrator 1 with zeroing (FIG. 3), and the pulse arriving at the inputs of the installation of zero of integrator 1 and counter 6 pulses, sets them to zero condition.

Thus, the installation in the zero state of the integrator 1 occurs at that moment in time when the input integrable signal is zero or. the minimum value, therefore, during the installation time in the zero state of the integrator 1, the loss of input information is absent or will be minimal. After the end of the pulse

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In the event that the output signal of the OR 13 of the driver 12 does not decrease the output integrated signal to zero or to a certain minimum value during the time interval, the AND 17 element of the driver 12 is activated, from which counter 6 is turned on from counter 6 the numbers of the range of numbers inputted to the element OR 13. From the output of the element AND 17, the signal through the element OR 15 enters the waiting generator 16 of pulses, which forms the pulse of the installation of the zero state of the integrator 1 and the counter 6 (Fig. ).

In the second partial circuit design, the elements OR 13 and AND 17 can be replaced by comparators, the first inputs of which should receive the output signal from Sr1, and the other inputs the reference voltages Ugp and UOH, respectively (Fig. 2).

One cycle of operation of inte- paTopal 1 with zeroing is considered. During this cycle, the input signal was integrated, the result of integrating this cycle as a digital code was recorded in the second counter.

7 and until it is set to the zero state is in the counter 6. After the next integrator cycle 1, the digital code in counter 7 is increased and continues until the end of the integration time.

The number of operation cycles of integrator 1 during integration into the input signal depends largely on the average value of the input signal and the integration time. The integration process is terminated by the device when the signal from the presetter 8 is stopped.

8 the moment when the signal at the output of setpoint 8 disappears, the key 11 is closed, the unit 4 records information (digital code) from the second counter 7, corresponding to the integration result, and the second counter 7 is set to zero with a command from the delay element 3. The delay element must delay the pulse coming from the setpoint 8 of the integration time for a time.

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The ranges of the integrated signal and the integration time for a given integrator (its devices can be large and are limited to Q only by the number of bits in counter 7 and in memory;

Formula of invention

jr 1. An integrated device containing a series-connected integrator with zeroing and a comparator, the first counter, the output of the KOTopoi o are connected to the input of a digital-to-analog converter, and the second counter and setpoint integrator, characterized in that, in order to improve the accuracy and increase the integration time, 25 a pulse generator, a delay element, a recording block, a reset pulse shaper, a threshold block and a key connected between the device input and the integrator input with 30 reset, are entered, the output is set The integration time ticker is connected to the control input of the key, the recording input of the storage unit and through the delay element connected to the zero input input of the second counter and the first control input of the reset pulse generator, the information input of which is connected to the output of the first counter, and the output connected with the inputs of the installation .Q zero of the integrator with the reset of the first pulse counter, the counting inputs of nepBoi o and the second counter are connected to the output of the pulse generator, and the inputs of the beginning of the count are connected to the output of the comparator, For setting the reference voltage of which is connected to the output of the digital-to-analog converter, the output of the second counter is connected to the input of the storage unit, the output of which is the output of the device, and the threshold unit is connected between the input of the device and the second control of the reset pulse generator.

2. The device according to claim 1, characterized in that the shaper of the ejection pulses comprises the first and second elements AND, the first and second elements OR, and the waiting 1 generator im 5

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iiy | ji.bcoB, the output of which is the output of the reset pulse shaper, the first input of the first element OR in the first control input of the shaper of the reset pulse, the second and third inputs are connected respectively to the outputs of nepBoi o and the second And output, and the output connected to the input of the waiting pulse retreparopa, the output of the second element OR is connected to the first input of the first element AND, the second input of KOTopoi o is the second control input of the reset pulse shaper, whose information input is connected to the combined inputs of the second element Comrade OR and I.

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Claims (2)

Claim 1 . An integrating device containing a series-connected integrator with zeroing and a comparator, the first counter, the output of which is connected to the input of the digital-to-analog converter, as well as the second counter and the integration time adjuster, characterized in that, in order to increase the accuracy and increase the integration time, it is introduced a pulse generator, a delay element, a storage unit, a reset pulse generator, a threshold unit and a key connected between the input of the device and the input of the integrator with a reset, the output is set The time integration indicator is connected to the control input of the key, the recording input of the storage unit and, through the delay element, is connected to the input of the zero counter of the second counter and the first control input of the reset pulse generator, the information input of which is connected to the output of the first counter and the output is connected to the inputs of the integrator zero by resetting the first pulse counter, the counting inputs of the first and second counters are connected to the output of the pulse generator, and the inputs of the beginning of the counting are connected to the output of the comparator, the input is SETTING reference voltage is connected to 'the output of the digital to analog converter, the output of the second counter is connected to the input of the memory unit, whose output is the output device, and threshold unit connected between the input device and the second control input of the reset pulse. 2. The device according to claim 1, characterized in that the reset pulse shaper contains the first and second AND elements, the first and second OR elements, and a waiting generator 1613731 pulses, the output of which is the output of the reset pulse generator, the first input of the first OR element is the first control input of the reset pulse generator, the second third inputs are connected respectively to the outputs of the first and second AND elements, and the output is connected to the input of the waiting pulse generator, the output of the second OR element is connected to the first input of the first AND element, the second input of which is the second control input of the reset pulse shaper, the information input of which is connected to the combined moves second OR and I. Figure 1 FIG. 3 Editor A.Kozrriz Compiled by S. Belan Tehred L. Oliinyk Corrector S. Cherni Order 3990 Circulation 560 Subscription VNIIIPI of the State Committee for Inventions and Discoveries at the State Committee for Science and Technology of the USSR 113035, Moscow, Zh-35, Raushskaya nab., 4/5 Production and Publishing Plant Patent ”, Uzhhorod, st. Gagarina, 101