SU1614099A1 - Single-shot vibrator - Google Patents

Description

The invention relates to radio engineering. The purpose of the invention is to reduce the level of nonlinear distortion of the output signal

while maintaining high speed adjustment. The device contains an oscillating circuit 1, a discrete variable capacitor (DKPE) 2, a second block of keys 6 made on semiconductor diodes, a third block 7 keys made on electromagnetic relays, a reversible counter 24. The purpose of the invention is achieved due to the initial tuning of the oscillating circuit 1 using the second block 6 keys and DKPE 2, the subsequent replacement of the second block 6 keys on the third block 7 keys and additional minor adjustment of the oscillating circuit 1. 1 Il.

1614098 A1

16 C Vros

3

1614098

four

The invention relates to radio engineering and can be used in the selective paths of radio equipment for various purposes.

The purpose of the invention is to reduce the level of nonlinear distortion of the output signal while maintaining a high speed adjustment.

The drawing shows an electrical structural diagram of the device for automatic tuning of the oscillating circuit.

The device for automatic tuning of the oscillating circuit contains an oscillating circuit 1, a discrete variable capacitor 2 (DKPE), an amplitude detector 3, an analog-to-digital converter (ADC) 4, the first 5. the second 6, made on semiconductor diodes, the third 7. made on electromagnetic relay, and the fourth 8 key blocks, the generator 9 clock pulses, the first 10, second 11. third 12 and fourth 13 keys, blocks 14 OR, first 15, second 16 and third 17 triggers, first 18, second 19 and third 20 comparators, first 21, second 22 and third 23 registers, reversible counter 24 and frequency divider 25.

Device for automatic adjustment of the oscillating circuit works as follows.

In the first cycle of operation by the device, the signal from the amplitude detector 3, which is the envelope of the high-frequency signal taken from the tuned oscillatory circuit 1, is converted at each step of operation of the device using the ADC 4 into a digital code. The first comparator 18 generates a single signal at one of its outputs when A>> B, and at the other when A <B, where A and B are digital codes arriving at its inputs.

Code B, rewritten into the second register 22 from the outputs of the first register 21, is delayed by one cycle. In this case, the following digital code is written in the first register 21. Thus, in registers 21 and 22, information is generated about the amplitudes of the adjacent steps of the resonance characteristic, where code A corresponds to the next one, and code B to the previous device operation cycles.

Changing the capacitance of the DKPE 2. i.e., switching its branches according to a binary law with the help of the second key block 6 initially switched on, is produced by a reversible counter 24 operating in addition mode and controlled by the first key 10 by the generator 9. The frequency of these pulses is determined , the speed of the diode key elements included in the second key block 6, and can be made quite high.

In the monotonous movement along the ascending branch of the resonance characteristic, code A is always greater than code B. Therefore, through the open signal A> B, the first block o keys 5 in the second register 22 constantly records information.

After reaching the extreme point, the next cycle of operation in the first register 21 provides information on the amplitude of the voltage step following the extremum (code A), and in the second, information on the amplitude of the extremum (code B). Since code A becomes less than code B, the signal at output A> B of the first comparator 18 changes to zero, closing the first key block 5 and prohibiting writing to the second register 22. Thus, information about the amplitude of the extremum is recorded in the second register 22.

The use of a diode key system ensures a high tuning speed during the first cycle of the device operation.

The appearance of a single signal at the second output Α ^Ζ Β of the first comparator 18 provides, through the second trigger 16, a change in the diode key system DKPE 2 to a relay, reducing the pulse repetition rate at the input of the reversing counter 24 in accordance with the speed of the relay key elements in the third block of keys 7 and moving to the second cycle of work. The division factor of the frequency divider 25 is selected based on the specific ratio of the response times of various types of key elements in the DKPE 2 branches.

Due to the change in the type of key elements in the branches of the DKPE 2, a detuning of the oscillating circuit 1 occurs, the sign and magnitude of which are unknown in advance. The amount of detuning of the oscillatory circuit 1 is determined using the second comparator 19. To do this, at the end of the first tuning cycle, the fourth key block 8 is opened and the next amplitude information is recorded in the first register 21 and the third register is clocked from the output of the frequency divider 25 23 - the previous step. If at output A <B of the second comparator 19, the zero signal does not change to a single signal, then code A is greater than shoe B, i.e. the tuning frequency of the oscillatory circuit 1 is located to the left of the resonant frequency on the ascending branch of the resonance characteristic and with each step of about 5

1614098

6

to the resonant frequency. If the signal changes to unity, this means that the tuning frequency of the oscillating circuit 1 is located to the right of the resonance point on the descending branch of the characteristic and with each step in the same direction moves away from the resonant frequency .. In this case, you need to change the direction of movement, i.e. . change the mode of operation of the reversible counter 24, which is provided by the signal 10 of the third trigger 17.

The third comparator 20, which compares the current amplitude code and the extremum code, serves to determine the moment of equality of these codes, which determines the end of the tuning process as a whole by turning off the generator 9 by this signal.

Reducing the nonlinear distortion of the output signal is achieved by using the oscillating circuit 1 of high-speed semiconductor diode switches in the adjustment process 20, and in the process of adjusting the oscillating circuit 1 and its subsequent operation electromagnetic relays that do not distort the input signal form 25.

Claims (1)

Claim A device for automatic tuning of an oscillating circuit, containing a series-connected oscillating circuit, an amplitude detector, an analog-to-digital converter, a first register, a first key block and a second register, a first trigger, a reversible counter, a third register, a discrete variable capacitor whose output connected to the control input of the oscillating circuit, a clock pulse generator, the output of which is connected to the control inputs of the analog-to-digital converter and the first and second regis The ditch, and the control input is connected to the output of the first trigger, the installation input of which is connected to the installation inputs of the reversible counter and the third register and is the installation input of the device for automatic tuning of the oscillatory circuit, which is in order to reduce the level of non-50 output signal distortion while maintaining a high tuning rate; a second key block, connected in semi-5 conductor diodes, and a third key block, made on electromagnetic relays, first key in series and OR block, in series second key and frequency divider are introduced in parallel; connected in series the first comparator and the second trigger, connected in series the second comparator and the third key, connected in series the third comparator and the fourth the key, the fourth block of keys, while the inputs of the first, second and third comparators are interconnected and connected to the corresponding outputs of the first register and the inputs of the fourth key block, whose outputs are connected to the corresponding inputs of the third register, the outputs of the second register are connected to the corresponding first inputs and The third comparators, the first output of the second trigger is connected to the control inputs of the first key and the second key block, the output of the clock generator is connected to the inputs of the first and second keys whose output of the fourth key is connected to the input of the first trigger, the second output of the second trigger is connected to the control inputs of the second, third and fourth keys, the third and fourth key blocks, the output of the frequency divider is connected to the second input of the OR block and the input 35 of the third register control, the output of the OR block is connected to the counting input of the reversible counter, the setup input of the first trigger. Connected to the setup inputs of the second and third triggers and the second register, the outputs of the third register are connected to the corresponding second inputs of the second comparator, the output of the third key is connected to the input the third trigger, the inputs of the second key block are connected to the corresponding outputs of the reversible counter, and the outputs to the corresponding control inputs of the discrete capacitor variable th capacitance of the third flip-flop output is connected to the control input of the reversible counter.