SU1608659A1 - Digital follow-up frequency multiplier - Google Patents

Abstract

The invention relates to computing and can be used in devices processing frequency sensors. The purpose of the invention is to increase the accuracy of multiplication. The digital tracking frequency multiplier contains a controlled oscillator of 1 clock pulses, a driver of 2 pulses, a first controlled frequency divider 3, a counter 4, a register 5, a second and a third controlled frequency divider 6, 7, and a phase detector 8 interconnected functionally. The difference between the frequencies of the input signal and the signal from the output of the controlled frequency divider 7 is detected by the phase detector 8, the output signal from which is fed to the control input of the 1 clock pulse generator, the change in the output frequency of which allows to compensate for the error of the output signal. 1 il.

Description

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31608659

The invention relates to computing and can be used in signal processing devices of frequency sensors.

The purpose of the invention is to increase the accuracy of multiplication.

The drawing shows the functional scheme of the multiplier.

The digital tracking frequency multiplier contains a controllable, generator

1-stroke pulses shaper

2 pulses, first control # 1 divider 3 frequencies, counter 4, register 5,

the second 6 and third 7 controlled divisible 5 walks multiplied frequency nf j, and

heat frequency and phase detector 8, functionally interconnected,

The multiplier works as follows, 20

Pulses of frequency f, generated by the oscillator 1 clock pulses, are fed to the input of the second controlled divider 6 frequency and, through the first divider 3, to the clock input of the counter 25 4, After a time interval equal to

its control input is given by code n, its output is formed by a signal with frequency f, which includes the error in determining the period, which is found in the fact that the frequency f does not fall off with the input frequency f

f highlighted

frequencies or phases between f and

with the phase detector 8, the first input of which receives a signal from the driver of the generator 2. The output signal of the detector 8 is fed to the input of the frequency generator 1, the frequency change of which allows the output signals of the generator 2 to completely phase out and divide 7, the latter means the complete ideality in phase (and even more so in frequency) of the signals f and f |, which characterizes the absence of an error in the frequency multiplier generation.

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the period of the input signal T, chike 4 will be formed code number

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where n is the code set on the control inputs of the first 3 and third .7 frequency dividers. At the end of the input signal period, the control input of the register 5 from the imaging unit 2 receives a recording resolution pulse and the result N from counter 4 is written to register 5. With the same signal, the counter 4 is reduced to zero. During the next periods The input signal of the counter 4 and the register 5 work in a similar way, as a result of which the output of the register 5 forms a code proportional to the divided by the n period of the input signal. Since this code arrives at the control inputs of the second divider 6, and a pulse ffl is applied to its input, the frequency of the output pulses of the device is equal to.

f.

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 - nf

N

At high frequencies of the input signal f or at large values of the multiplication factor n, the filling of the counter 4 is significantly reduced.

which leads to significant discreteness in determining the divided period, t, e, to a large margin in the formation of the number N and, accordingly, the output, multiplied frequency.

Almost completely eliminate the error of discreteness allows the phase automatic frequency control (PLL) ring, which includes the third controlled frequency divider 7, the phase detector 8 and the controlled clock pulse generator 1.

Since the input of the divider 7 is

the frequency nf j ,, goes on, and on

0

five

its control input is given a code n, at its output a signal with a frequency f is formed, which includes the error in determining the period, which is expressed in that the frequency f does not coincide with the input frequency f

f selects frequencies or phases between f and

0

5 0 5 0

five

with the phase detector 8, the first input of which receives a signal from the output of the imager 2. The output signal of the detector 8 is fed to the input of the frequency control of the oscillator 1, the frequency change of which allows the output signal of the imager 2 and the divider 7 to fully equalize full phase identity (and especially frequency) of the signals f and f |, which is characterized by the absence of an error in the frequency multiplier conversion.

Claims (1)

Invention Formula A digital tracking multiplier, a frequency containing a clock generator, first, second and third controlled frequency dividers, a counter, register and pulse generator, whose input is the information input of the multiplier, and the output of the pulse shaper is connected to the register recording enable input and the setup input The counter, the counting input of which is connected to the output of the first controlled splitter frequency, the setup inputs of which are the inputs of the multiplication factor multiplication, the bit outputs tchika connected respectively to the input information register, The discharge outputs of which are respectively connected to inputs of the second mounting .s controllable frequency divider, whose output is the output of the multiplier and the input 516086596 The BTcjporo controlled frequency divider by the installation inputs of the third control is connected to the input of the first controllable frequency dividers, the input of which is a frequency divider, which is differently connected to the output of the second control t The frequency divider, multiplication accuracy is multiplied, the pulse former is connected to the electronic detector, and the clock generator by the first input of the phase detector, impulses made in the form of a controlled second input of which is connected to the output generator, the output of which is connectedThe third controlled divider is connected to the input of the first controlled de-, Q frequency, and the output of the phase detector is a frequency player; the installation inputs are connected to the control input of the generator connected to the clock pulse pulser. Red Compiled by V.Gusev iKTop A.IandorTekhred M.KhodanychCorrector S.Cherni Zach 13 3617 Circulation 564 Subscription The State Committee on Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5