SU1601573A1 - Apparatus for ultrasonic inspection - Google Patents

Abstract

The invention relates to non-destructive testing by an ultrasonic method and can be used in installations for automatic quality control of materials and products. The aim of the invention is to increase the reliability of control by detecting a single extended defect from several small consecutive defects during registration and determining their conditional size. The use of additional blocks and new connections in the device allows us to isolate a series of (P-K + 1) pulses from a defect, during which the condition K of pulses sufficient for detecting a defect from the N expected pulses from the minimum detected defect is fulfilled. For the same series of pulses, the presence of a single extended defect or several small additions of follow defects in the direction of movement of the converter is determined. The device allows you to select a series of sync pulses H, which allows to determine the conditional size of the defect. 2 Il.

Description

The invention relates to the field of HP-met1 control by an ultrasonic method and can be used in installations for the automatic control of the quality of materials and products.

The aim of the invention is to increase the reliability of control by detecting a single extended defect from several small follow each other paLTpt ™ °

Figure 1 shows the block diagram of the device; figure 2 - timing diagrams, we explain his work,

The device for ultrasonic (US) control contains a synchronizer 1 connected in series, the first circuit AND 2 and the first trigger 3, the output of which is connected to the second input of the first circuit AND 2 connected in series the second trigger 4, the second circuit AND 5, block 6 calculations the first OR circuit 7 and the first counter of 8 pulses, the output of which is connected to the second input of the first circuit OR 7 using GGTG lo f ° automatic alarm device 10 defects (ASD), speed sensor 11 and series-connected meter 12 acoustic, contact tire Formiro wagon 13 whose second input is connected to speed sensor 11, code converter 14 and storage unit 5 whose first output is connected to the second input of computing unit 6, the second output to the second input of the first counter 8 impulses and rRTs connected third trigger 16, third I circuit 17 and the OR 18 circuit, the output of which is connected to the first input of the execution unit 9 along

therefore, the fourth trigger 19 is connected. The fourth circuit is AND 20 and the pulse counter 21 is pulsed, the output of which is connected to the first input of the third trigger 16 of the fifth circuit AND 22 and the driver 23. Connected to the first input / fourth trigger 19 and the fifth circuit AND 22 to the input ACA 10. to the second input of the second circuit AND 5 and to the output of the synchronizer 1, the second input of the fourth circuit AND 20 the output of the first circuit AND 2 is connected to the Third inputs of the computing unit 6 and the first counter 8 pulses, the output of the ASD 10 is connected to the first input of the second trigger - pas 4 to the fourth inputs of block 6 you 8 counts of the first counter and the second inputs of the fourth trigger 19 and the third AND 17 circuit. The output of the OR 7 circuit is connected to the second inputs of the first and second triggers 3 and 4 and to the fifth input of the 6th computation block, the second inputs of the third the second circuit OR 18 is combined and connected to the first counter of 8 pulses, the input of the second counter 21 of pulses is connected to the second output of the storage unit 15. the second. the input of the fifth circuit And 22 is connected to the output of the trigger 16. And the output to the second input of the executive unit 9 and the third input of the second counter 21 pulses

Figure 2 shows the diagram 24 - 33 signals from the blocks of the device.

The device operates as follows: S n - j; ,

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HwS defect registration. The values of the numbers N and K correspond to the definitions.:; OGGDGN s o and aGustic - contact through the bus driver 13

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five

10 to 20

25

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. 13

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K and T. sat. From the output of the memory flea 15, the codes of these numbers are fed to the information (second) inputs of the calculation unit 6 and the counter 8 pulses.

The first input of the first circuit AND 2 receives V pulses 24 (FIG. 2) synchronization from synchronizer 1. and at B- oP °; ° VnDH pulses from the output of the first P P ZPG on the coincidence in time of these pulses at the 0 output of the AND circuit 2 a pulse that enters the inputs of the preliminary Record of the calculation unit 6 and the counter 8 pulses. This impulse records the numbers m and K in them. The pulses 25 from the defect from the output of the ASD 10 are fed to the counting counter 8 pulse input and are subtracted from the preset 20 K number when the K-th pulse arrives from the defect 8 pulse count working out a loan. indicating the "effect and arriving at the second input of the circuit

25 the first impulse from the defect with the ASD 10 overturns the second trigger 4. the signal from Ghod which permits the passage

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  PGHGII gaps in the pulse sequence from the defect at the output of the computing unit 6 a pulse is generated which is fed to the first input of the circuit

dp With the output of the circuit OR 7 pulse corresponding to ° in time or pulse with

45 no returns the device to the initial counter temperature of the counter 8 pulses 26. in accordance with the execution of the K program, N is fed to the second input of the third trigger.

ASD 10 through the third scheme And 17 and vtoruk; the OR 18 scheme at the first entrance of the Executive Director, OGaGp Ge-eG ".

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6 l o.a9inatre of the second counter 21 da. pulses (diagram 29. fig.).

The second input of the fourth trigger 19 receives impulses from the defect with ASD 10 and overturn it. The fourth trigger 19 returns to the initial state by the clock pulse 24. The signal 31 from its output allows the passage of pulses 30 from the former 23 through the fourth AND 20 circuit (diagram 32, figure 2) to the first input of the second counter 21 pulses, which t is a record of the number K from the storage unit 15.

For example, program 3 of 6 is set, where K 3, N 6. Then the first counter 8 pulses for the third and fifth pulses 25 of the 5 defect does not work, since there are four passes between the fifth and ninth pulses and the device is reset by a pulse from block 6 calculations Pulse counter 8 is activated for the twelfth and seventeenth pulses (diagram 26, figure 2), since here condition 3 out of 6 is satisfied. The eighteenth and nineteenth pulses are not fixed. Thus, with a defect of eleven sync pulses 29, during which program 3 of 6 is being executed, two pulses, twelfth and seventeenth, are emitted on the counter 8 pulses.

The first incoming impulse (twentieth) from the output of counter 8 overturns the third trigger 16, and a series of impulses from the defect from the twelfth to the ninth to the eleventh pulse is selected on the second OR 18 circuit (diagram 28, figure 2). Consequently, the first input of the executive unit 9 receives a series of pulses P- (K-1), where P 8 is the total number of pulses from the defect, during which condition 3 of 6 is fulfilled, and the second input of the executive unit 9 receives a series of sync pulses 29 from the twelfth to the twenty second, allowing to determine the conditional size of the defect by the formula

,

where V is the speed of movement of the converter; F is the frequency of the following clock pulses;

H - the number of sync pulses in the series. The former 23 generates service pulses 30, which coincide in frequency with the sync pulses 24, but lagging in time by 0.5 - 1 Tel, where Tel is the sync pulse 24.

The fourth trigger 19 through the fourth circuit AND 20 permits the passage of pulses from the imaging unit 23 (diagrams 31 and 32, FIG. 2) to the first input of the second pulse counter 21, which is written to the last number K. The second pulse counter 21 is triggered only when K of impulses from a defect appears (Diagram 33, Fig. 2); otherwise, if there is a pulse from a defect, the number K is restored in the second counter by 21 pulses from the former 23.

If there are K gaps in the signals from the defect, a pulse 33 is formed at the output of the second counter 21, which returns the third trigger 16 to its initial state. With this, the pulse from the defect and sync pulses are stopped, and the device is ready to receive the next information.

Claims (1)

The invention The device for ultrasonic control, containing a serially connected synchronizer, the first AND circuit and the first trigger, the output of which is connected to the second input of the first circuit I. A serially connected second trigger, second AND circuit, computing unit, first OR circuit and first pulse counter, output which is connected to the second input of the first OR circuit, the executive unit, the automatic defect detector, a speed sensor and an acoustic contact connected in series, an audio contact meter the globalizer, the second input of which is connected to the speed sensor, the code converter and the storage unit, the first output of which is connected to the second input of the computing unit, the second output to the second input of the first pulse counter, the synchronizer output is connected to the input of the automatic defect indicator and to the second input of the second circuit And, the output of the first circuit AND is connected to the third inputs of the computing unit and the first pulse counter, the output of the automatic defect detector is connected to the first input of the second trigger and to the quarter The inputs of the computation unit and the first pulse counter, and the output of the first circuit OR are connected to the second inputs of the first and second triggers and to the fifth input of the computation block, characterized in that, in order to increase the reliability of the control, it is equipped with serially connected third trigger, third circuit And the second OR circuit, the output of which is connected to the first input of the execution unit, connected in series by the fourth the trigger, the fourth And circuit and the second pulse counter, the output of which is connected to the first input of the third trigger, the fifth And circuit, and the former, whose input is connected to the first inputs of the fourth And trigger and the synchronizer output, the output to the second input {fourth AND circuit, the second inputs of the third {trigger and second OR circuit) are combined and {connected to the output of the first pulse counter, the second inputs of the fourth trigger and the third AND circuit are combined and connected to the output of the automatic signaling indicator, the second the input of the second pulse counter is connected to the second output of the storage unit, the second input of the fifth circuit AND is connected to the output of the third trigger, and the output is connected to the second input of the execution unit and the third input of the second counter pulses.