SU1596325A1 - Generator of correlated normal numbers - Google Patents

Abstract

The invention relates to computing and can be used in simulating normal correlated random processes and digital codes with given variance and correlation coefficient. The aim of the invention is to increase the speed of generation of correlated normal numbers with given variance and correlation coefficient. To achieve this goal, the registers of the numbers 11 and 12, the block of elements OR-NOT 14, the switch 15, the element OR-NOT 17, the noise generator 1, the delay line 3, the comparators 4 and 5 are entered into the generator. The output sequence is formed in the adder 16. 1 il.

Description

ate G

The invention relates to computing and can be used in simulating normal correlated random processes and digital codes with given variance and correlation coefficient.

The purpose of the invention is to increase the speed of generation of correlated normal numbers with given variance and correlation coefficient.

The drawing shows a functional diagram of the generator of correlated normal numbers.

The generator of correlated normal numbers contains a noise generator 1, a generator of 2 clock pulses, a delay line 3, comparators 4 and 5, an element EXCLUSIVE OR 6, an element AND 7, triggers 8 and 9, a register 10, registers 11 and 12 numbers, a multiplier 13, block of elements OR NOT 14, switch 15, adder 16 and element AND LINE 17.

The device works as follows.

In the initial state, the number in register 11 is a number that determines the correlation coefficient, and in the number 12 register is a number that determines the variance of the generated sequence of correlated normal random numbers. Triggers 8 and 9 are in an arbitrary state, and in register 10 is written some initial number. The noise generator 1 forms at its output an analog high-frequency random signal arriving at the inputs of the comparator 5 and delay line 3, the delay time of which is chosen on the condition that the signals at its input and output do not correlate. Thus, at each time point, two weakly correlated analog high-frequency random signals are fed to the inputs of comparators 4 and 5. Random two-bit uniformly distributed numbers are formed at the outputs of comparators 4 and 5, for which the threshold values of comparators 4 and 5 are chosen based on the same of the logical logic zeros and ones at their outputs.

The two-bit code P at the outputs of the EXCLUSIVE OR 6 element and the AND 7 element (the highest bit of this code corresponds to the output of the EXCLUSIVE OR 6 element, and the low-order one to the output of the AND 7 element) is binomially distributed. In fact, due to the uniform occurrence of logical zeroes and ones at the outputs of comparators 4 and 5, the state of P 10 appears in 50% of cases, and P 01 or P 00 in 25% of cases. To synchronize work

The device as a whole serves as a generator of 2 clock pulses, forming a periodic pulse sequence. With the arrival of the next sync

Pulse code P is recorded in triggers 8 and 9, and in register 10, the output code of adder 16 is fixed. At each clock cycle, depending on the code P recorded in triggers 8 and 9, the output code of multiplier 13 is left or

0 unchanged (P 10), either the number written in the 12th register (P 01) is added to it, or the number written in the 12th number register (P 00) is subtracted. For this are the block of elements OR NOT 14, switch 15,

5 adder 16 and element OR NOT 17. Block of elements OR NOT 14 when the logical zero exists at the output of the trigger 8. inverts the register code of the 12th number. If a logical unit is present at the output of trigger 8, then a zero code is generated at the output of the block of elements OR NOT 14. Switch 15 delivers to the second input of the adder 16 either a direct register code 12 of the number (if at the output of trigger 9 is a logical one), or

5 code from the output of the block of elements OR NOT 14 (if the output of the trigger 9 is a logical zero). When subtracting (P 00), the logical unit from the output of the OR-NOT element 17 is added to convert the inverse code to the additional to the lower bit of the adder 16.

Thus, at the output of the adder 16, a sequence of correlated normal numbers with given

5 variance and correlation coefficient. Denoting the code of the next number by Xk, the register code of the 11 number (correlation coefficient) through g, the register code of 12 numbers through V, we can express the variance of the generated MOL number sequence as Dx V / 2 (1-r2).

Thus, specifying the necessary correlation coefficient r and the dispersion parameter V 2Dx (1-r), we obtain the sequence

Claims (1)

5 random correlated normal numbers with given characteristics. The claims of the generator of correlated normal numbers, containing a clock generator 0 pulses, two triggers, the first register, a multiplier and an adder, the output of the clock generator is connected to the clock input of the first trigger, the output of the multiplier is connected to the input of the first term of the adder, the output of which is connected to the information input of the first register, characterized in that speed increase, a noise generator, a line, a delay, two comparators, an EXCLUSIVE OR element are introduced into it. the element AND, the element OR NOT, two registers, the block of the elements OR-NOT and the switch, the output of the noise generator is connected to the input of the first comparator and through the delay line with the input of the second comparator, the output of the first comparator is connected to the first inputs of the element EXCLUSIVE OR and the element AND, the second inputs of which are connected to the output of the second comparator, the output of the element AND is connected to the information input of the first trigger, the output of the element EXCLUSIVE OR is connected to the information input of the second trigger, the clock input of which is connected to the output house clock generator and a write enable input of the first register, whose output is connected to the input of the first multiplier the multiplier, the input of the second factor of which is connected to the output of the second register, the direct output of the first trigger is connected to the control input of the switch and with the first input of the element OR-NOT, the second input of which is connected to the direct output of the second trigger and the first input of the block of elements OR-NOT, the second input of which is connected to the output of the third regitra and with the first information input of the switch, the second information input of which is connected to the output of the block of elements OR NOT, the output of the switch is connected to the second input of the adder, the third input of which is connected to the output of the element OR NOT, the output of the adder is the information output of the generator.