SU1596270A2 - Statistic analyzer of finite difference of signal phase - Google Patents

Abstract

The invention relates to a radio measuring technique and can be used to determine the statistical characteristics of a signal phase. The purpose of the invention is to improve the measurement accuracy of the estimates of the characteristic function of the finite difference of the first order of the signal phase with a change in the frequency ω of the signal under study. The goal is achieved by compensating for the phase shift V .ΩΤ at both a constant frequency and a change in the frequency of the signal under study, where V is the real parameter of the characteristic function

Τ is the delay time when forming the finite difference of the first order. Compensation improves the accuracy of measurement of the estimates of the characteristic function of the finite difference of the first order of the signal phase. In the statistical analyzer of the finite difference of the first order of the phase of the signal in the preparatory cycle, the phase shift V. Ω .Τ is determined by the obtained distribution, which is inherent to the finite difference, and compensated by means of a controlled phase shifter at the analyzer input. 2 Il.

Description

The invention relates to a radio metering technique and can be used to measure the statistical characteristics of a random signal phase and is an improvement to a statistical analyzer of a finite difference in signal phase.

The purpose of the invention is to increase, exactly. measurement of the estimates of the characteristic function of the finite difference of the first order of the signal phase with a change in the frequency of the signal under study.

Fig. 1 shows a structural diagram of a statistical analyzer of a finite difference of the first order of phases of a signal; Fig 2 - timing charts of the statistical analyzer.

The statistical analyzer of the finite difference of the first order of the phase of the signal contains a controlled phase shifter 1, a reference oscillator 2, an analog storage unit 3, the first sampling and storage unit 4 (VHR), the second sampling and storage unit 5, the first analog-to-digital converter (ADC) 6, the second analog-to-digital converter 7, the first accumulating adder 8, the second accumulating adder 9, the first reading unit 10, the second reading unit 11, a gate generator 12, a persistent storage unit 13, digital-analogue converter (DAC 1 controlled voltage divider 15, controlled clock generator 16. The input of the statistical analyzer of the finite difference of the first order of the signal phase is the combined inputs of the controlled phase shifter 1 and the former 2 of the reference oscillator Output of the controlled phase shifter I is connected to the input analog storage unit 3, the output of which is connected to the combined inputs of the first and second channels of the converter, in each of which the first and second swarm nodes sample and store 4 and 5, the first and second analog-to-digital converters 6 and 7, the first and second accumulating adders 8. and 9, the first and second reading units 10 and He. The combined gating inputs of the sample and storage unit and the analog-digital converter of the first and second channels are respectively connected to the first and second gates of the gating pulse generator 12, the signal inputs of which are connected to the output of the shaper 2 of the reference fluctuations are the outputs of accumulating adders 8 and are connected to separate inputs of a permanent fuse block 13, the output of which is connected to a series-connected digital-to-transform the body 14 and the controlled voltage divider 15, the output of which is the control input of the controlled phase shifter 1. Combined gating inputs of accumulating adders 8 and 9 and clock inputs of the persistent storage unit 13, digital-to-analog converter 1A and controllable voltage divider 15 connected to the measuring time circuit. The first and second outputs of the controlled oscillator 16 clock pulses are connected respectively to the first and second clock inputs of the analog storage unit 3, in which the first clock input is combined with the clock input of the driver 2 of the reference oscillation. The control input of the controlled voltage divider 15, the control input of the gate generator 12 strobe pulses and the input of the controlled generator of 16 clock pulses are combined and form the control input of the statistical analyzer In the initial state, the reading blocks 10 and II accumulating accumulators 8 and 9, DAC 14 cleared, the code corresponding to the first value of v is written to the first register of the voltage-controlled divider 15 voltage, and the second register of this digital-to-analog converter is zero. The voltage at the output of the controlled voltage divider 15 is zero and fa The base shift introduced by the controlled phase shifter 1 is wounded to zero. The statistical analyzer of the final difference of the phase of the signal works as follows: The signal under investigation is fed to the analyzer input (Fig.2a); V (t) lJ. sin (a) t + (t (t)). The measurement cycle begins with the appearance of the leading edge of the pulse in the measurement time circuit. The real parameter of the characteristic function v is set using an analog storage unit 3 and a controlled oscillator of 16 clock pulses. The discrete values of the JJ sensor signal are written to the analog storage unit 3 during the period of the input signal with a frequency f set by the controlled oscillator 16 clock pulses, and then read from frequency V f set by the same clock pulse generator. Thus, at the output of the analog storage unit 3, the segments of the signal under study are multiplied v times the frequency and phase (figo). LZU (t) (t) j and a duration equal to the period of the input signal divided by v. The reference oscillator 2 is an analog delay line which, by delaying the signal under study for time v, generates a reference oscillation. The gate sampler 12 generates two quarter-shifted sequences of strobe pulses from the reference oscillation, the frequency of which is equal to the signal frequency at the analog output. memory block Zo The beginning of these gating pulses is delayed by time {relative5 1

for the moment when the signal under study passes through zero from the region of negative values to the region of positive values (Fig.2d, d),

The VHR 4 integrates the signal under investigation into the signal input with a frequency and phase multiplied by v times during the time of the strobe pulse at its gating input. As a result of the integration, at the output of the VHR 4 the signal is received:

U sin vwt + vcf; (t) j. dt - cos vcd; f + V (,) (t, -) J-cos va) t | + + vaj + V4 (t, + 2). Since the pulse at the gate of the VHF 5 is shifted relative to the gate of the VHR 4 by a quarter of the period, then at the output of the VH5 5 we get a signal ti + 3r / fv v / exf and sin vwt + vy (t) dt and 5 samples and storage are fed to the ADC 6 and 7v inputs. At the same time, the ADC 6 and 7 start at the end of the gating pulse, Tov, by the time integration is completed in the UHF 4 and 5 °. After the analog-digital conversion to the output is completed. impulse corresponding to the accumulating adder, summarizes the code generated at the output of the ADC with the code recorded to date in the accumulating adder. The first analyzer operation cycle ends on the trailing edge of the first pulse at the input of the Measurement Time. Thus, if during the measurement time 2N periods of the input signal are realized, digital codes of numbers will be obtained in accumulating adders: A (v) 7i Z-cosrvgi (t) + vtJtJ. N i4)) -: Z-sin v f (t) + Vl; it,. where X.Xv), B (v) are the estimates of the real and imaginary parts of the characteristic function of the random process η, cf (t) + wr. If we assume that A (v),

962706

B (v) are estimates of the real and imaginary parts of the characteristic function of the random process tfCt), then for symmetric distribution laws with zero mean value B (v) 0, which is the case of the process C - (f (t) - - - u; C , you can write characteristic function

ten

0 (v) X (v) + jB (v) $ (v) .exp (jvw)

Claims (1)

A (v) -t-jS (v) J expCjv o. Since S (v) 0, then 6 (v) A (v) exp (jva; o) (v) cos vcvT) VX sinvo / tl Hence A (V) A (V) cosvwC, B (v) A (v ) sinvwi ;. Solving this system better with respect to ujf :, we obtain the relation Jc - arctg, “For any V, we can determine t and then carry out automatic compensation of the phase shift ujf. Compensation is made as follows. Two numeric codes are fed to the address bus of block 3: the first from accumulating adder 8 to the upper half of the bits of the address bus of block 13, the second from accumulating adder 9 to: the lower half of the bits of the address bus of block 13. When the difference from 1 to O pulse in the measurement time circuit, the code is read from the memory cell 13, the address of which corresponds to the code on the address bus of block 13, to the DAC register 14. The D / A converter 14 is also started after the digital-analog conversion to the input of the controlled divider 15, for example voltage is applied proportional to vwi). At this the preparatory stage (Fig. 2b) ends and a direct measurement of the counts of the characteristic function of the end function begins; phase difference signal. Upon the arrival of the next leading edge of the pulse in the measurement time circuit (Fig. 2b), a reset occurs. writing the code from the first DAC11 register, the equalizer 15 has a voltage in the second register of this DAC, and the first register of the DAC records the code corresponding to the next value of v, and the voltage at the DAC output 14 is divided into a controlled divider 15 voltage The division factor the controlled voltage divider corresponds to the code recorded in the second DAC register of the voltage divider 15 being controlled. The output voltage of the controlled voltage divider, corresponding to wt, is applied to the control section of the controllable phase shifter 1, which introduces a phase shift equal to cJu. The control of the unit 14, the divider 15, is carried out in such a way that the output of the output controlled divider 15 is stressed Voltage per measurement cycle does not change, while during the measurement time the controlled 1 1st phase shifter 1 introduces a constant phase shift and; Φ obtained in the first preparatory phase of measurement. In the second and subsequent measurement cycles, a signal of the form V (t) eU sin u; t + "v (t) -tS" is supplied to the input of block 3, and voltages proportional to the values of v, t are obtained at the inputs of the water economy equipment 4 and 5 ) cos {vi t) + vajC-vart, V (v, t) (t) + vajfr-vurC i The accumulating adders 8 and 9 receive codes of numbers proportional to the real and imaginary components of the characteristic function of the final first-order difference phase of the signal with compensated phase shift ujD Anv),. (v, t), where N is the number of codes summed by the glow adder during the pulse time of the Measurement Time. The measurement results stored in the memory registers of accumulating adders 8 and 9 are indicated in reading blocks 10 and 11. The presence of estimates of the characteristic function, measuring HHbix for different values of the real parameter v, allows analytically determining the statistical characteristics of the finite difference of the first phase order of the signal. Thus, the introduction of a persistent storage unit, a digital-analog converter, a controlled voltage divider and a controlled phase shifter can improve the accuracy of measurement of the estimates of the characteristic function of the first-order finite difference signal at an unknown input signal frequency Formula of the invention The statistical analyzer of the final signal phase difference by Aut. No. 1422182, characterized in that, in order to improve the measurement accuracy of the estimates of the characteristic function of the finite difference of the first the phase of the signal when changing the frequency of the signal under study, a controlled phase shifter, a controlled voltage divider, a digital-to-analog converter and a constant transceiver unit, whose inputs are respectively connected to the outputs of accumulating adders, are output, the output is connected to a series-connected digital-analog converter and a controlled divider voltage, vpsod which is connected to the input of the controllable controlled phase shifter, high-frequency input and output of which are connected respectively The input of the analyzer and the input of the analog storage unit, the clock inputs of the permanent storage unit of the digital-analogue converter and the controlled voltage divider connected to the control input of the statistical analyzer are connected to the measurement time circuit. FIG.