SU1584082A1 - Analog-digital phase shifter - Google Patents

Abstract

The invention relates to a measurement technique and can be used to create phase-shifting devices for harmonic and quasi-harmonic signals in a wide frequency range. The aim of the invention is to improve the accuracy of setting the phase shift of the output signal. The analog-digital (AD) phase shifter contains an analog-digital converter (ADC) 1, switch 2, registers 3 and 4, a digital-to-analog converter (D / A converter) 5, pulse shaper 6, pulse frequency multiplier 7, pulse generator 9, a comparison unit of 10 codes, counter 11. Shaper 6, together with multiplier 7, generator 8, element I, and counter 11, form a recirculator synchronizer with automatic frequency tuning of the input signal. Comparison unit 10 is used when reading samples of the signal from the recirculator to select the desired I-th clock pulse. The AD phase shifter allows you to adjust the phase shift of the input signal in steps determined by the multiplier 7 of the input signal in the range of phase shifts determined by the volume of the recirculator memory. The AD phase shifter allows you to track slow changes in the frequency of the input signal, which eliminates the need to recalculate the signal delay to the phase shift value. 1 il.

Description

The invention relates to a measurement technique and can be used to create phase shifters for harmonic and quasi-harmonic signals in a wide frequency range.

The aim of the invention is to improve the accuracy of setting the phase shift of the output signal.

The drawing shows a structural analog-digital phase shift.

The analog-to-digital phase shifter contains an analog-to-digital converter fs tel 1, switch b, first 3 and second 4 registers, digital-to-analog converter 5, shaper 6 pulses, multiplier 7 pulse frequency, generator of 8 pulses 20 ss, element And 9, block 10 comparison codes, the counter 11.

Analog-digital phase shifter works as follows.

The analog input signal arrives at the first input of the analog-digital converter 1 and 6 pulses at the input of the former. The latter, together with the multiplier 7 of the pulse frequency, the generator of 8 pulses, 30 And 9 elements, and the counter 11, form a synchronizer of the recirculator with automatic adjustment by the frequency of the input signal. The pulse generator 6 converts the input signal 35 into a sequence of square Pulses, which are fed to a multiplier 7 pulse frequency, having a multiplication factor K. The output signal of a multiplier 7 frequency 40 Pulse following - sampling pulses is a sequence of pulses of duration T "with a period where T 0 is the oscillator clock frequency period of 8 pulses, 45 pulses, Tc is the period of the input signal, and Ta} NT0, where N is the memory volume of the first register 3 of the recirculator consisting of a switch ora first register 2 and 3.50

A sequence of sampling pulses is used to take samples of the input signal and record them by a recirculator, and also goes to the set input of the counter 11. At. c, This at the output of the high bit of the counter 11 is set to zero potential, the element And 9 is unlocked, the clocking pulses from the output of the generator of the 8 pulses start to come to the synchronization input of the first register 3. A sample of the input signal from the output of the analog-to-digital converter 1 through the switch 2, opened at the control input by the sampling pulse, is recorded in the first register 3, where the circulation process begins. The recirculator memory (N words) is associated with a recalculation factor of counter 11, which is (N-1) 2tfl, and an additional register is included in the sample ring. The bit size of the counter 11 is m + 1, due to the fact that the high bit of the counter 11 is used to control the AND 9 element.

I

Counter 11 counts the clock pulses and with the arrival of the (N-1) -ro pulse at the high-order output, the signal level changes, element 9 closes and the circulation process stops until the next sampling pulse arrives, after which the second sample of the input signal is recorded and the process circulation is repeated. Due to the difference in the value of the memory volume of the recirculator (N) and. the conversion factor of the counter 11 (N-1), the sampling and sampling periods of the input signal differ by one clock cycle, i.e. for each circulation, the recorded sample of the input signal is shifted relative to the sampling pulse by one clock cycle. Consequently, by reading the information into the second register 4 with the i-th pulse following the sampling pulse, you can get a signal with a time delay (To + Te), and the phase of the delayed signal is respectively tfgblx (To + T0) / Tc. The code comparison unit 10 is used in reading samples of the signal from the recirculator to extract the desired 1st clock pulse. The width of the counter 11 per unit exceeds the size of the block 10 comparison codes.

From the output of the second register, the delayed input signal is digitally fed to the input of the digital-to-analog converter 5, where it is converted into an analog signal with a phase shift, the value of which is given by the code supplied to the control inputs of the bits of the code comparison unit 10. In this case, the phase adjustment step of the output

signal cf -juu 1 „-hhv /, ic

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360 ° (T9 + T))) / TC. Since, then, by setting the value of if, it is possible to determine the value of K, at which the error in setting the phase of the output signal is minimal: K (fe / 360 ° - -T0 / Tt. Due to the fact that T0 "TC, the error of the device does not exceed 0.1 - 0.3tf0npH maximum phase shift values of the output signal

m «ks 360 ° (VT«) WEDP with the adjustment step (360 / K.

Thus, the proposed analog-to-digital phase shifter allows adjusting the phase shift of the input signal with a step determined by the multiplication factor of the frequency multiplier of the input signal in the range of phase shifts determined by the amount of the memory of the circulator. In addition, the proposed phase shifter operates in an automatic mode over the entire frequency range of the input signals and makes it possible to track slow changes in the frequency of the input signal, which eliminates the need to recalculate the signal delay to the phase shift value.

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Claims (1)

Invention Formula An analog-to-digital phase shifter containing serially connected analog-to-digital converter, a switch and a first register, the outputs of which bits are connected to. corresponding bits of the second inputs of the switch, the control input of which 25 0 , connected to a second input of an analog-to-digital converter, the first input of which is an input of an analog-digital phase shifter, serially connected a second register and a digital-analog converter, the output of which is an output of an analog-digital phase shifter, pulse generator, counter and element It is due to the fact that, in order to improve the accuracy of the phase shift installation, serially connected between the first and second 5 analog-digital converter inputs pulse shaper and pulse multiplying frequency multiplier; code comparison unit, the output of which is connected to the synchronization input of the second register; the control input of the switch is connected to the installation input of the counter, the counting input of which is connected to the synchronization input of the first register1 and the output of the element AND, 5, the first input of which is connected to the output of the counter's low discharge, the outputs of the lower bits of which are connected to the inputs of the corresponding bits of the code comparison unit, the control inputs of the bits of which are the control input of the analog-digital phase shifter, the output of the pulse generator is connected to the second input the multiplier of the pulse frequency and the second input of the element I, and the outputs of the switch bits are connected to the inputs of the corresponding bits of the second register.