SU1538143A2 - Statistic analyzer of final difference of signal phase - Google Patents

Abstract

The invention relates to a radio measuring technique and serves to determine the statistical characteristics of signal phase fluctuations. To improve the accuracy of determining the statistical characteristics of the investigated step ΔV of quantizing the real parameter of a random process ΔV = ϕ / 2F _M , where F _M is the maximum deviation of phase fluctuations from its average value, the range of 2 F _M phase fluctuations is measured during the analysis time entered by digital phase The detector and the table recorded in the Permanent Storage Unit determine the value of the optimal quantization step, which is used during the next analysis time. The use of the optimal quantization step of the real parameter makes it possible to reduce the methodological error in determining the statistical characteristics of the fluctuations of the phase of the signal to values (10 ^-4 - 10 ^-5 )%. 3 il.

Description

The invention relates to a measurement technique, can be used to measure the statistical characteristics of a random phase of a signal, and is an improvement of the invention according to the author, # 1422182.

The mean value of the random variable e) Vx is called the characteristic function 9 (v) of the random variable x, namely

e (v) m, teJVX} A (v) + JB (v), (l)

where S (v) is the characteristic function;

v

ha

A (v), B (v)

real parameter

characteristic

functions;

mathematical sign

waiting;

estimates, respectively, of the real and imaginary parts of the characteristic function

It is known that by measuring the estimates of the real and imaginary components of the characteristic function for various values of the real parameter v, one can determine

SP

with

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31538143А

statistical characteristic of a random process under study. for example

6- --- + 4 fr П A () Г 2f B (iav) V ,,, 6- | + H) - I - U J, (-) (2)

where С is the standard deviation of the random process under study;

UV is the quantization step of the real parameter v of the characteristic function; i is an integer. The purpose of the invention is to improve the accuracy of determining the statistical characteristics of the random process under investigation.

Fig. O1 is a structural diagram of a statistical analyzer of a finite phase difference of a signal; figure 2 - timing charts of the statistical analyzer.

The statistical analyzer of the final phase difference of the signal contains an analog storage unit 1, a reference oscillator 2, a digital peak detector 3, a permanent storage unit 4, a buffer register 5, a code adder 6, a controlled oscillator 7 clock pulses, a frequency divider 8, the first 9 and 10 second elements of the sample and storage, the first analog-to-digital converter 11, the second analog-to-digital converter 12, the first accumulate

the adder 13, the second accumulating adder 14, the first reading indicator 15, the second reading indicator 16, the driver 17 of the gating pulses

The inputs of the statistical analyzer of the final phase difference of the signal are the combined inputs of the analog storage unit 1, Shaper 2 reference oscillation and the first input of a digital peak detector 3, the second input of which is connected to the output of shaper 2 reference oscillation. The output of the digital peak detector 3 is connected to serially connected permanent storage unit 4, buffer register 5, adder 6 and cods. The output of adder 6 codes is connected to the input of the controlled oscillator 7 clock pulses, the first and second outputs of which are connected respectively to the first and second clock the inputs of the analog storage unit 1, which has the first

0

five

0

Q

This input is combined with a clock input of the driver 2 of the reference oscillation. The gating input of the adder 6 codes combined with the input of the frequency divider 8 and connected to the measurement time circuit. The output of the frequency divider 8 is connected to the clock input of the permanent storage unit 4, the synchronization input of the digital peak detector 3 and to the zero inputs of the buffer register 5 and the adder 6 codes. The output of the analog storage unit 1 is connected to the combined inputs of the first and second conversion channels, in each of which the first 9 and second 10 samples of sampling and storage, the first 11 and second 12 analog-to-digital converters, the first 13 and second 14 accumulating adders, the first 15 and second 16 reference indicators. The gating inputs of accumulating adders 13 and 14 are connected to the Measurement time circuit. The combined gating inputs of the sample and storage element and the analog-digital conversion of the first and second conversion channels are connected respectively to the first and second outputs of the gate generator 17, the first input of which is combined with the controlled code generator 7 clock pulses, and the second input is connected to the output of the driver 2 reference oscillation.

Analog storage unit 1 is designed to change the real parameter of the characteristic function v by multiplying the phase of the signal under study. To do this, discrete values of the input voltage for one period of the signal under investigation are first recorded in the analog storage unit, and then this information is read at a read pulse frequency, v times. Higher sampling frequency The operation of the analog storage unit is identical to that of a known analyzer.

The reference waveform generator 2 serves to form the reference signal and is analogue

delay line. Moreover, the time constant of the delay line determines the parameter of the studied final difference of the signal phase

4 (t) / Jv (t) f (t) - v (t-f). (3)

Digital peak detector 3 is designed to measure the magnitude of phase fluctuations. At the output of the digital peak detector 3, a digital code is generated that is proportional to the magnitude of the phase fluctuations of the signal under study.

In the persistent storage unit 4, a table is written corresponding to twice the value of the maximal deviation from the average random variable (and the optimal quantization step dv of the real parameter.

In the table, the correspondence between the range of fluctuations of the signal under study and the optimal value of the quantization step is the parameter of the characteristic recalculation and one-shot, the fork function is obtained using the expression

/ Jv ff / (2 K dO,

(four)

where b k

JP

RMS value of the random process under investigation;

the coefficient relating the maximum deviation from the mean value of phase fluctuations cfmn 6, i.e. .ipm Kj.p.6- It was established experimentally that the methodological error reaches its minimum of 10 4-1СГ% with such a determination of the quantization step value & v real parameter. The input of block 4 receives a digital code corresponding to the address of the memory cell, in which the code of the quantization step value of the characteristic function parameter is written. Reading from memory occurs when the signal drops from one to zero at the clock input of the block.

The buffer register 5 is used to store the quantization code of the parameter of the characteristic function & v during the entire analysis time (Fig. 2) The register is reset by a drop from one to zero at the zero input. Code adder 6 is used to set the characteristic parameter.

5381436

function Y. It consists of an adder, a one-shot that generates a short negative pulse when the signal level drops at a gating input from zero to one, and a memory register, which is written to at a drop from one to zero at the one-shot output. The contents of the memory register are reset when the signal level at the zeroing input is changed from one to zero.

The controlled generator of 7 clock pulses generates two sequences of clock pulses, one with a frequency f -, a friend - with a frequency

uh

five

ten

15

v. s The generator is controlled by a digital code and can be implemented from series-connected pulse generators and controlled by a frequency multiplier code.

Frequency divider 8 generates the analysis time signal and is a counter with a predetermined coefficient

five

0

five

0

five

A negative negative pulse is observed when the signal level drops from one to zero.

The 17 gating pulse shaper generates at its outputs two pulse sequences shifted relative to each other by a quarter period, the duration of which is equal to half the signal period at the output of the analog storage unit. The shaper's operation is based on the principle of frequency multiplication in the PLL system and the subsequent formation of a phase shift of 90 °, for which the multiplication factor is chosen equal to 4 Vo

Elements 9 and 10 of the sampling and storage of the integrating type are designed to integrate the voltage arriving at their input in a time equal to the duration of the pulse arriving at the gating input. The sample and hold elements are analogue integrators with reset. som Reset integrators occurs on the leading edge of gating pulses.

Analog-to-digital converters (ADC) 11 and 12 of any type are supplemented by a single-shot that forms the beginning of the conversion cycle on the falling edge of the pulse at the output of the ADC gating. At the end of the conversion cycle, the ADC 11 and 12 are formed and 1

71

its synchronization output is the pulse of the end of the conversion.

Each of accumulating adders 13 and 14 consists of adders, a memory register, which is written when a pulse is received at the synchronization input of the accumulating adder and if there is a logical unit at the gating input, and a single vibrator, which forms a reset of the memory register when the front one appears of the pulse front at the gating input

The readout indicators 15 and 16 provide a digital indication of the counts of the characteristic function A (v) and B (v) and consist of a decoder and a digital indicator,

In the initial state, the reading indicators 15 and 16, accumulating adders 13 and 14, the buffer register 5 and the adder 6 codes are zero, the zero code is on the output of the digital peak detector 3, and the output of the frequency divider 8 is the potential of logic zero. The zero code from the output of the adder 6 codes prohibits the operation of the controlled generator of 7 clock pulses, which, in turn, prohibits the operation of the analog storage unit 1. This position is maintained until the appearance of a logical unit in any code bit at the output of the digital peak detector 3

Statistical analyzer finite difference of the phase of the signal works as follows.

The signal under study is fed to the analyzer input and then follows the input of the reference oscillator 2 and the first input of the digital peak detector 3. The delayed signal from the output of the reference oscillator 2 arrives at the second input of the digital peak detector 3, which during the analysis time ( Fig. 2c) measures 2tfm-magnitude of fluctuations of a finite difference of the 1st order of the signal phase. At the end of the analysis time (Fig. 2b), a digital code appears at the output of the digital peak detector 3, corresponding to a value of, for example, 360 °

The measurement, directly from the readings of the characteristic function, begins with the appearance of the front image of the second pulse. Analysis time

0

five

0

five

81438

(Fig. 2c) at the output of frequency divider 8 In this case, the information from the memory cell, the address of which is the digital code at the output of the digital peak detector 3, is read into the buffer register 5, the table corresponding to the magnitude of the phase fluctuations and the optimal quantization step AV of the real parameter the characteristic function is written in block 4o. Thus, in buffer register 5, the entire code analysis time () is the digital code of the optimal quantization step value & v real parameter, in this example Av 0.5

On the leading edge of the pulse at the input of the Measurement Time, the accumulating adders 13 and 14 are zeroed out and the contents of the buffer register 5 are added to the contents of the register of the adder 6 codes. Adder

6 codes works in accumulating mode-4-me. Thus, at the output of the adder 6 of codes there is a code of the current value of the real parameter v

 i 4v, where I is the number of the stage (fig. 2b) or the number of the pulse at the input of the measurement time during the analysis time (fig. 2b). The meaning of the coefficient i coincides with its designation in formula (2) and i varies from 1 to n, where n is the required number of samples of the characteristic function and the division factor of the frequency divider 8. For example, n 10.

Consider, for example, the measurement of the counts of the characteristic function in the third stage () with the optimal quantization step dv 0.5 in this case from the output of the adder 6 codes to the input of the controlled oscillator

7-pulse pulses the digital code of the number v zsv-i 1, 5. At the output of the controlled oscillator 7 clock pulses, two sequences of pulses are formed: one with a frequency f, the other with a frequency

vf j l, 5fg. Both of these sequences of pulses arrive at the clock inputs of the analog storage unit 1.

The analyzed signal (Fig „2a) is fed to the input of the analyzer. The period of the investigated signal is recorded in analog storage unit 1 with a sampling frequency equal to the frequency fЈ of the signal supplied to the first

0

five

0

five

0

five

915

a clock input from the first output of the controlled oscillator 7 clock pulses, and is read with the frequency of the signal received from the second output of the controlled oscillator 7 clock pulses (v-f3 1,5fg). Thus, a piecewise-pulse signal is formed at the output of block 1 with phase and frequency multiplied v (1.5) times (Fig. 2d) "From the signal coming from the output of the driver 2 of the reference oscillation, the driver of the 17 strobe pulses forms two sequences of pulses shifted one relative to the other by 90 ° element s 9 and 10 sample and hold. Moreover, the pulse duration is equal to half the period of the signal read from the analog storage unit (FIG. 2d, d, e) „

Elements 9 and 10 of the sample and storage integrate the signal arriving from the analog storage unit 1 during the action of the pulses arriving at the gating inputs from the formaker 17 gating pulses

As a result of the integration at the outputs of elements 9 and 10, the sampling and storage get two estimates, proportional to

V (dv.i, t) cos (dv. I-if (t), (5)

V f4v-i, t) sin (dv i-q (t)), (6) I

For this case

V (0.5-3, t) cos (0.5-3-4 (t)),

V (0.5-3, t) sin (0.5-3-cf (t)).

The integrated voltage values from the outputs of elements 9 and 10 are sampled and stored at the inputs of ADCs 11 and 12. The start of ADCs I and 12 is performed on the falling edge of the pulses fed to the input of the gates from the driver 17 gates,. immediately after the end of integration. After the end of the analog-digital conversion, the ADC 11 and 12 form a pulse at the output of the Conversion End. This pulse arrives at the synchronization input of the corresponding accumulating adder 13 or 14, which causes the addition of the code generated at the ADC output to the code recorded in the memory register of the accumulating adder 13 or 14.

43 0

The measurement of 1 (3) counts of the characteristic function ends when the 1st (third) pulse is completed. The measurement time in this analysis cycle (Fig. 2b, c).

Thus, numeric codes of numbers proportional to the real and imaginary components of the characteristic function will be obtained in accumulating summaries 13 and 14:

A; (WY-1} (7)

B, (du i) Ј2 V (avi.t). N P ° s l

(eight)

where N is the number of codes summed by the accumulating adder during the pulse duration. Measurement time at the gate input. For the example in question

A3 (0.5-3) 1 iS (0.5-3, t)

five

0

five

0

5 0 5

Ve (0.5-3) Ј 1 (0.5 3, t). E o

The measurement results in the memory registers of accumulating adders 13 and 14 are indicated in the readout indicators 15 and 16. On the falling edge of the pulse of the analysis time (Fig. 2b), the buffer register 5 and the adder 6 codes o are reset. Thus, the statistical analyzer The final phase difference of the signal is ready for new measurements.

The presence of estimates of the characteristic function, measured at various values of the real parameter v, allows analyzing the required statistical characteristics of the finite difference of the signal phase in an analytical form. The choice of the optimal quantization step av of a real parameter reduces the methodological error of the analyzer and at the same time normalizes the number of necessary samples of the characteristic function, which leads to a gain in either the speed or the statistical accuracy of measuring the samples of the characteristic function.

Thus, the introduction of a digital peak detector, a persistent storage unit, a buffer register, a code adder, and a frequency divider can improve the accuracy of determining the statistical characteristics of the signal under investigation, the Invention Formula

Statistical analyzer of the final phase difference of the signal according to the author. No. 1422182, characterized in that, in order to improve the accuracy of determining the statistical characteristics of the phase of a signal, serially connected digital peak detector, a permanent storage unit, a buffer register and a code adder, and a frequency divider connected to its input circuit Measurement time, the first input is digital 15

The second peak detector is connected to the input, and the second input is connected to the output of the reference oscillator, the output of the frequency divider is connected to the synchronization input of the digital peak detector, the clock input of the permanent storage unit and the inputs of the zeroing of the buffer register and the code adder, the output of the latter is connected to the control input clock generator, and the input of the gating of the code adder - with the input of the frequency divider and the zeroing inputs accumulates accumulators of adders.

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p pp pppg pp p ppppppp nnnnnnnnn t

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Claims (1)

The claims • Statistical analyzer of the final phase difference of the signal according to ed. St., No. 1422182, characterized in that, in order to improve the accuracy of determining the statistical characteristics of the phase of the signal, series-connected digital-c are introduced into it; the first peak detector, read-only memory, buffer register and code adder, as well as a frequency divider with a circuit connected to its input. Measurement time, the first input of the digital 1st peak detector is connected to the input, and the second input to the output of the reference oscillator, output the frequency divider is connected to the synchronization input of the digital peak detector, the clock input of the permanent storage unit and to the inputs of zeroing the buffer register and the adder codes, the output of the latter is connected to the input of the controlled generator ovyh pulses and input gating 'of the adder! codes - with the input of the frequency divider and the inputs of zeroing the accumulating adders. - 2tsh _v hail - 4V 2 (f ha, deg 4V 2φπι, deg Z5v . ---- 2 ifm, hail - 2tfm,. hail - _ _Ί dV 2h®, hail 4V 0 0 7.5 24 fifteen 12 24.5 7 72.5 2. 240.5 0.7 0.5 360 8 22 15,5 12 0 o about about in about " " • · · • · · about · · 1 180 8.5 21 16 eleven 27.5 7 1 10 2 275 0.7 1,5 120 9 20 16.5 AND 28 6 110.5 1,5 275.5 .0.6 2 90 9.5 19 17 eleven in about • · · • ABOUT · • * “ Oh oh • · " 2,5 72 10 18 17.5 10 32,5 6 150 1,5 320 0.6 3 60 10.5 17 18 10 33 5 150.5 1 320.5 0.5 3,5 fifty eleven 16 18.5 10  in · • · · • · about • · “ 321 0.5 4 45 11.5 16 19 9 40 5 200 1 321.5 0.5 4,5 40 12 fifteen 19.5 9 40.5 4 200,5 0.9 322 0.5 5 36 12.5 14 • about a • about · about · " »· · " about · •. " o o ♦ • · · 5.5 32 thirteen 14 21 9 51 4 220 0.9 358.5 0.5 6 thirty 13.5 thirteen 21.5 8 51.5 3 220.5 0.8 359 0.5 6.5 27 14 thirteen oo "·" • "· "· · • about e • about · 359.5 0.5 7 25 14.5 12 24 8 72 3 240 0.8 360 0.5 Figure 1 and g Iwy ^. WWWW / WVWVVWW \ A a a ft L -,, —1step ¢ = 4 / 7Η —....... ЗымйДЧ8 ΑΓ-AS Stage 2. Г ^I АГг: _l ^TWT ™ * ~ / у ---- ν Л>'1 / ΤΛ-η / - ^> ^{ Fshp J1- Γ-η_αιπππ g pp n ppppppp ppppppp n p -fa- .. G ____ ΓΊ ppppp ppp ppppppp ppppp nnnJ ηΐ ~ -'Σ7Σ ~: ΤΉ -. . t * 4 5 stage f-Avd ChetopG ^ oG! . Hell·! - '-.......- = ir-—: _f FIG. Z