SU1591012A1

SU1591012A1 - Digital frequency multiplier

Info

Publication number: SU1591012A1
Application number: SU894600673A
Authority: SU
Inventors: Nikolaj A Kamynin; Evgenij I Kostryukov
Original assignee: Kb Aviat I
Priority date: 1989-11-01
Filing date: 1989-11-01
Publication date: 1990-09-07

Description

The invention relates to computing and can be used in analog synchronization devices.

digital converters. The aim of the invention is to expand the scope of the digital frequency multiplier due to the possibility of expanding the boundaries of the working range of input frequencies. Digital frequency multiplier contains shaper 1 pulses, the first element And 2, accumulating adder 3, the first controlled divider 4 frequency generator 5 clock pulses, the second element And 6, the second controlled divider 7 frequency, first 8, second 9. third 10 and fourth 11 registers, two triggers 12,13, the third element And 14, two subtractive counters 15,16 and the fifth register 17, interconnected functionally. 1 il.

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The invention relates to computing and can be used in synchronizing devices analog-digital converters.

The purpose of the invention is the expansion of the scope due to the possibility of expanding the boundaries of the working range of input frequencies.

The drawing shows the functional diagram of the digital frequency multiplier.

The multiplier contains a driver 1 pulses, the first element And 2, accumulating adder 3, the first controlled divider 4 frequency generator 5 clock pulses, the second element And 6, the second controlled divider 7 frequency, the first 8, second 9, third 10 and fourth 11 registers, the first 12 and second 13 triggers, the third element And 14, the first 15 and second 16 subtractive counters and the fifth register 17, interconnected functionally.

The multiplier works as follows.

The input sequence signal with a period of T _{x is} fed to the input of the shaper 1, which generates control pulses of duration T _x received at the input of the element And 2.

The clock pulses from the generator 5 are fed through the element 6 to the counting input of the controlled frequency divider 7 and to the input of the accumulating adder 3 through the second input of the element 2. In registers 8 and 9, the numbers a and β are pre-recorded, respectively.

Over the time interval T _x, the input of accumulating adder 3 is fed N = Τ _χ · ίο pulses, where ίο is the frequency of the clock generator 5. To the input of the controlled divider 4 frequencies comes Νι = <x / 2 ⁿ pulses, where n is the number of digits of the adder 3

The counting inputs of the subtracting counters 15 and 16 receive N2 = ^ -pulses.

At the end of time T _{x, the} number N2 from the subtracting counter 15 is copied to register 10 and determines the division factor of the controlled frequency divider 7, at the output of which the pulses follow with a period

Then

t - ^P1 - ^Ν '«-Two ·" ^OUT 2 "· 0. · ίο 2 ^η β

because

0: £ α <2 ^η -1,

that Designating ao = -¾. 2 get Your ⁼ t _x ·, those. frequency output signal

By changing a and β one can get practically any, as a whole and fractional, multiplication factor with sufficient accuracy, since ao changes with a step of 1/2 ^P.

Changing the working range of the multiplier as follows.

The front of the pulse from the output of shaper 1 into the subtractive counter 15 loads the value Νη from register 11, which determines the lower limit of the range, and subtracts 16 from the register 17 load the value Νβ, which determines the upper limit of the working range. The counters begin to count the pulses from the output of the controlled divider 4 frequencies, the number of which is equal to N2. Assume N2> Νβ. then, when the subtractive counter 16 reaches the zero state, the transfer pulse from its output sets the trigger 13 to one state. If the input frequency is within the operating range, the pulse from the output of shaper 1 passes through the second input of element 14 and writes a new value N2 to register 10. At the same time, the logical signal "1" from the output of the trigger 13 runs on the information input of the trigger 12, and the pulse from the driver 1 is supplied to the synchronous input of the trigger 12, which is set to one and allows the pulse 5 of the generator to pass the output of the output signal . On the trailing edge of the pulse trigger 13 is set to the zero state.

The input frequency is above the cutoff frequency, i.e. N2 <Νβ. Then at the time of the formation of a pulse by the shaper 1, the counter 16 does not generate a transfer pulse, the trigger 13 remains in the zero state and the write pulse to the register 10 does not come through the element 14. Accordingly, at the moment of arrival of the pulse to the synchronous input of the trigger 12, a zero is written into it, which prohibits the impulses from the generator 5 to the divider 7 and the formation of the output signal.

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The input frequency is less than the cutoff frequency, i.e. N2> Νη. During operation of the circuit, the counter 16 generates a transfer signal, setting the trigger trigger 13 to one state, and the transfer pulse of the counter 15, since the number recorded in it is less than the number of pulses received at the input, resets the trigger 13 to the zero state. Thus, at the time of passage of the pulse from the driver, the element And 14 is closed by a logic level "0" from the output of the trigger 13 and writing to the register 10 is not performed. The trigger 12 is also set to the zero state, prohibiting the formation

output signal.

Claims

Claim

A digital frequency multiplier containing a pulse shaper, a clock pulse generator, the first and second triggers, the first and second controlled frequency dividers, the first - the fourth registers, accumulating adder and the first, second and third elements And, the output of the clock generator is connected to the first inputs of the first and the second element 14, the second input of the first element And is connected to the output of the formation of pulses, the input of which is the frequency input of the multiplier, the direct output of the first trigger is connected to the second input v The first element And whose output is connected to the clock, the input of the second controlled frequency divider, the output of which is the output of the multiplier, the output of the first element And is connected to the counting input of the accumulating adder, the setup inputs of which are connected respectively to the bit outputs of the first register, the output of the accumulating adder is connected to the clock the input of the first controlled frequency divider, the setup inputs

which is connected respectively to the bit outputs of the second register, the bit outputs of the third register are connected respectively to the setup inputs of the second controlled frequency divider, the output of the pulse shaper is connected to the first input of the third element,

And, the output of which is connected to the resolution input of the third register recording, which is due to the fact that, in order to expand the scope of application, due to the possibility of expanding the limits of the working range of input frequencies, the first and second subtractive counters and the fifth register, with the output of the pulse shaper connected to the enable inputs of the parallel recording of the first and second subtractive counters, the output of the first controlled frequency divider is connected to the counting inputs of the first and second subtractive counters, the transfer output ne The first subtractive counter is connected to the installation input to the "0" of the second trigger, the transfer output of the second subtractive counter is connected to the installation input to the "1" of the second trigger, the direct output of which is connected to the second input of the third And element and to the information input of the first trigger, the clock input of which connected to the clock input of the second trigger and to the output of the pulse shaper, the information input of the second trigger is connected to the logic zero bus, the bit outputs of the fourth register are connected respectively to the installation in odes first subtracter counter bit outputs of which are connected respectively to the data inputs of the third register, a fifth register bit outputs are connected respectively to inputs of the second subtractor mounting counter.