SU1589408A2 - Device for checking discrete channels - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to determine the failure state of a monitored discrete channel. The device contains an analyzer of 1 received signals, a counter of 2 errors, a block of 3 comparisons, a decoder of 4 measurement cycles, a reversible counter 5, a decoder of 6 state numbers, a block of 7 impulse delay lines, a block of 8 registers of numbers, OR elements 9-11, a counter 12 pulses, triggers 13, 14, element 15 and shapers 16, 17 pulses. The content of the reversible counter 5, according to the results of operation of blocks 1-4 and 6-10, reflects the state of the monitored discrete channel. Counter 12 monitors the channel time in the worst of the stationary states and generates a "No normal" signal. Blocks 13 - 17 block the operation of the device at the time of the channel change and prepare it for monitoring the newly connected channel. 1 il.

Description

I The invention relates to electro sshz, can be used in an up, the control of discrete channels and concerns the improvement of the device according to the author. St. No. 1142894.

 The purpose of the invention is to determine the call status of the monitored discrete channel.

I The drawing shows the structural and electrical diagram of the proposed device.

The discrete channel control device contains analyzer 1 received signals, 2 error counter, J5 bpok 3 comparisons, decoder 4 measurement cycles, reversible counter 5, decrypter 6 state numbers, block 7 impulse delay lines, block 8 registers of numbers, element OR 20 9, the first 10 and second 11 are the additional elements OR, the pulse counter 12, the first 13 and the second 14 triggers, And 15 elements, the first 16 and the second 17 pulse formers.

I The device works as follows,

I Selected n stationary states, the flow of which are statistical

The setting inputs of the error counter 2 and block 3 are warranted; and, through the second additional element OR 11, to the zeroing input of the pulse counter 12, as a result of which the error counter 2, the comparison block 3 and the pulse counter 12 are reset, and the reversible counter 5 goes to (i + 1) -e state. The signal from the reversible counter 5, corresponding to the (i + 1) My channel condition, goes to the output of the device, for example, to the data transmission equipment to reconfigure it to (1 + 1) -th mode of operation (not shown) and to the input of the decoder 6 state numbers, the signal from the (1 + 1) -th output of which goes to the (i + 1) -e inputs of the number setting register 8. and the number 7 of the pulse delay lines. .. With the (i + 1) -ro register of the block 8 of the number setting registers in the comparison block 3, the values N and N are written, and through the (1 + 1) th pulse delay line of the block 7 after the time T has passed a pulse to one of the inputs the decoder 4 measurement cycles, Thus, with the improvement of the state of the channel, its control will be wire-,

1 | 4niem. Each i-th state of Kana, i.e.

jiHe control time duration T ;, Set, one of the impulse lines of the block l delay 7, as well as the lower N} upper N limits of the number of errors recorded in one of the registers of the set 1 and the numbers of block 8,.

Channel dualities are considered unavailable 30, e de

the encoder of 4 measurement cycles for Wits. |, and corresponds to a definite value - goes to the installation input of the reversible counter 5, through the SHSh 9 element - to the installation inputs of the 2 error counter and the comparison unit 3, and through the second additional element OR 11 - to the zero reset pulse counter 12, in Re Erroneously received signals from the output Q as a result of which the counter is 2 errors, the analyzer unit 1 arrives at the input of the error counter 2 and is counted last during the time T, The measured number of errors N during the time T is compared in block 3 comparison with 45 values of N and N. With the arrival of a pulse from the output of block 7 HNmynbCHbrx delay lines corresponding to the end of T., to one of the inputs de50

encoder 4 measurement cycles, depending on the ratio of N ,, N, and N

g and 1.T N

i

N, N.,

.N,

three cases are possible: N 7 / N f.

If, then, at the output of the decoder, there are 4 measurement cycles in accordance with the Vits pulse, which through the first additional element OR S enters the summation input of the reversible counter 5, through the element IL11 9 - to the service 55

3 comparisons and pulse counter 12 are zeroed, and reversible counter 5 remains in the xth state. The signal from the reversible counter 5, corresponding to the i-1-fy channel state, is output to the device (in this case, the data transmission equipment remains in the previous mode of operation) and ita input of the decoder is 6 state numbers, the signal from the i-ro output is received ie, the inputs of the block of 8 registers of the task of numbers and the block of 7 impulse lines. Delay. From the i-ro register of the block 8 registers assigning numbers to block 3

the previous digits and N are recorded, and through the i-th pulse delay line of block 7, after the time T has elapsed, a pulse arrives at one of the inputs of the decoder 4

 comparison of N;

The setting inputs of the error counter 2 and block 3 are valid; input, and through the second additional element OR 11, to the zeroing input of the pulse counter 12, resulting in the error counter 2, the comparison unit 3 and the pulse counter 12 zeroing, and the reversible counter 5 goes to ( i + 1) -e state. The signal from the reversible counter 5, corresponding to the (i + 1) My channel condition, goes to the output of the device, for example, to the data transmission equipment for reconfiguring it to the (1 + 1) -th mode of operation (not shown) and to the input of the decoder 6 state numbers, the signal from the (1 + 1) -th output of which is fed to the (i + 1) -e inputs of the number setting register 8. and the block 7 pulse delay lines. .. With (i + 1) -ro of the register of block 8, the case of setting numbers in comparison block 3 records the values of N and N, and through the (1 + 1) -th pulse delay line of block 7 after the time T passes, a pulse arrives at one of the inputs decoder 4 measurement cycles. Thus, with the improvement of the channel condition, its monitoring will be wire,

 , e de

Q resulting in a 2 error counter, block 5

0

five

3 comparisons and pulse counter 12 are zeroed, and reversible counter 5 remains in the xth state. The signal from the reversible counter 5, corresponding to the i-1-fy channel state, is output to the device (in this case, the data transmission equipment remains in the previous mode of operation) and ita input of the decoder is 6 state numbers, the signal from the i-ro output is received ie, the inputs of the block of 8 registers of the task of numbers and the block of 7 impulse lines. Delay. From the i-ro register of the block 8 registers assigning numbers to block 3

the previous digits and N are recorded, and through the i-th pulse delay line of block 7, after the time T has elapsed, a pulse arrives at one of the inputs of the decoder 4

 comparison of N;

51

measurement cycles. Thus, in the unchanged state of the channel, it will be monitored during the previous time T ;.

If Nj7 N, then the pulse at the output of the decoder of 4 measurement cycles a pulse arrives at the input of the subtraction of the reversible counter 5 and, via the OR 9 element, at the installation inputs of the error counter 2 and the comparison block 3, causing the error counter 2 and the comparison block to zero. and the reversible counter 5 is transferred to the (il) -e state. The signal from the reversible counter 5, corresponding to (il) -My channel state, nocTyrtaeT to the output of the device (to reconfigure the data transmission equipment to (1-1) -th mode of operation) and to the input of the decoder 6 state numbers, signal c (il ) -ro of the output of which enters the (il) -e inputs of block 8 of the number setting registers and block 7 of pulse delay lines, C (il) -ro of the register of block 8 of the number setting registers and in block 3 of comparison the values

N

n

and

compare

N -1 and after

(i-l) -K

- - - J - l IM1Tu l b

After the time T f has elapsed, a pulse is sent to one of the inputs of the decoder for 4 measurement cycles. Thus, if the channel deteriorates, it will be monitored over time T - T.

If the channel is in

with .

states

and as a result, the control will determine what, then the signal from the reverse

counter 5, corresponding to this channel condition, goes to the decoder of 6 state numbers, the pulse from the additional output of which goes to the counting input of the pulse counter 12 and, through the first additional element 1shi 10, to the input of the summation of the reversing counter 5, the signal from the reversible counter 5, corresponding to the state, is fed to the input of the decoder of 6 state numbers. The measurement cycle is repeated with the previous T ;, N, N. If the channel state deteriorates again, then a pulse arrives at the subtraction input of the reversible counter 5, which transforms the reversible counter 5 into the state. At the additional output of the decoder 6 state numbers, the pulse is output and the process outlined above is repeated. By improving the condition of the channel or finding

0

five

0

five

it is in the same state () the pulse from the output of the decoder 4 measurement cycles is fed to the input of the summation. the reversible counter 5 (via the first additional ISH1 10) of its setting input, and through the second additional element OR 11 to the zeroing input of the pulse counter 12, as a result of which the pulse counter 12 is reset,

If in each of the ha of consecutive measurements on samples with a duration Tj the number of errors calculated by the counter 2 errors exceeds the limit for making a decision to go to the state, then with the arrival of the t-th pulse at the input of the counter 12 pulses calculated for (t- 1) pulses, counter 12 overflows, and the signal No channel (failure) signal from its output goes to the setup input of the first trigger 13, which is set to one state. The signal from the output of the first trigger 13 is fed to the first input element And 15 and the external equipment, providing a channel change (not shown). At the time of the changeover

0 (channel change) from the external device, a signal arrives at the second input of the element 15 and the input of the second pulse generator 17, which selects the leading edge of the incoming signal and resets the second trigger 14 to the zero state with an output pulse. The signal from the zero output of the second trigger 14 prohibits the operation of the 2 error counter.

Upon completion of the reconfiguration of the means, the first pulse shaper 16 selects the falling edge of the signal received from the external equipment through the element 15, the output pulse sets the first trigger 13 to the zero state (removes the result of the channel monitoring No channel norm) - the second trigger 14. The signal from the single output of the second

0 trigger 14 through the OR element 9 enters the installation inputs of the 2 error counter and the comparison block 3 and through the first additional element OR 10 - tia input of the summation of the reversing counter 5, as a result of which the error counter 2 and the comparison block 3 are zeroed and the reversible counter 5 goes to state. The signal from the reversible counter 5, respectively 5

0

i 1, the input of the Descriptor is 6 numbers of the state, the measurement of the quality of the connected channel is carried out at the values of And x T ,, N, N, If the quality of the new Channel is good (i), it remains connected, and the dal is monitored for its condition. If, however, in successive measurements of the quality of a connected channel on samples with a duration T, the number of errors SoKj counted by the counter 2 errors j exceeds the limit for making a decision to go to a state, then the process described above repeats the signal No channel norm to external hardware and health control of the newly connected channel.

formula of invention

i The control device of discrete auto-on channels No. 1142894, which is 25 k and so, in order to determine the failure state of the monitored discrete channel, the third output of the measuring cycle decoder is connected to the sum input of the reversible counter ZO. through entered

the first additional element OR, the additional output of the state number decoder is connected to the additional input of the element OR through the input-connected pulse counter, the first trigger, the AND element, the first pulse driver and the second trigger, zero output, the installation input and the reset input of which are connected respectively to the input prohibit the error counter, with the reset input of the first trigger and with the output of the input second pulse generator, whose input is connected to the second input of the AND element and is in the resetting signal of the discrete channel control device, the output of the fault state signal of which is the output of the first trigger, and the second and third outputs of the measurement cycle decoder are additionally connected respectively to the first and second inputs of the entered second additional element OR whose output is connected to the pulse counter zeroing input , the counting input of which is connected to the second input of the first additional element OR, the third input of which is connected to the single output of the second trigger ra.

Claims (1)

[Claim Discrete channel monitoring device by auto No. 1142894, with the exception of the fact that, in order to determine the failure state of the monitored discrete channel, the third output of the decoder of the measurement cycles is connected to the summing input of the [reverse counter through the first additional OR element entered, the additional decoder output number of statuses is connected to the additional input of the OR element through sequentially connected pulse counter, the first trigger, the And element, the first pulse shaper and the second trigger, zero output, installation input and input the reset of which is connected respectively to the input of the prohibition of the error counter, with the reset input of the first trigger and with the output of the introduced second pulse shaper, the input of which is connected to the second input of the And element and is the input of the reset signal of the discrete channel control device, the output of the failure state signal of which is the output of the first trigger , and the second and third outputs of the decoder of the measurement cycles are additionally connected respectively to the first and second inputs of the entered second additional element nt OR, whose output is connected to the zero input ’of the pulse counter, the counting input of which is connected to the second input of the first additional OR element, the third input of which is connected to the unit output of the second trigger.