SU1587654A1 - Addresing-switching device - Google Patents

Abstract

The invention relates to communication technology. The purpose of the invention is the elimination of loss of information from priority sources during switching. The device contains a drive 1, valves 2 and 4, a block of 3 signals of the reference frequency, register 5, keys 6 and 7, a counter of 8 states, a decisive block 9, a single pulse generator 10, a buffer register 11, elements 12, 23 - 26, counter 13 addresses, decoder 14, memory blocks 15 and 17, multiplexer 16, memory key 18, elements OR 19-21, counter 31 of the number of occupied storage areas of the memory. To eliminate the loss of information, a device 22 enumerates the addresses, elements 27 and 28, trigger 29, pulse generator 30, decoder 32, address multiplexer 33, and memory block 34. When receiving extra information with a service attribute NO (the beginning of the source), the device performs its processing by priorities. 1 il.

Description

The invention relates to communication technology and can be used in switching nodes of telegraph channels of high throughput.

The purpose of the invention is the elimination of information loss from priority sources during switching.

The drawing shows a structural electrical diagram of an address-switching device.

The address switching device contains a drive 1, an output distributor 2, a block of 3 reference frequency signals, an input distributor 4, an input register 5, an input key 6, an output key 7, a state counter 8, a decision block 9, a single pulse generator 10, a buffer register 11 , the first element And 12, the counter 13 addresses, the first decoder 14, the first memory block 15, the multiplexer 16, the second memory block 17, the memory key 18, the first, second and third elements OR 19-21, the counter 22 enumeration of addresses, the second, third , fourth, fifth, sixth and seventh elements And 23-28, t a trigger 29, a pulse shaper 30, a counter 31 of the number of occupied zones of the storage memory, a second decoder 32, an address multiplexer 33, a third memory block 34.

Address switching device operates as follows.

Information from M sources on H | data lines (M N) is fed to input registers 5. Input distributor 4, using signals from block 3, connects output registers 5 through input keys 6 to buffer register 11. When i-ro is connected to input register 5 ( where 0 £ ϊ έΗ) at the outputs of the buffer register 11 an information word will appear, consisting of the address part, in which the K-th number of the source of information is encoded (where О ί К М) of the actual information part and service information containing signs of the start of the NI source and her to CA KI (presence or absence of a logical unit in the corresponding bits addressable data word). In this case, the address part enters through the input of the address multiplexer 33 to the address input of the first memory block 15, the information part - to the input of the keys 18, a sign

NI - through the And 26 element to the control input of the address multiplexer 33, through the And 25 element - to the recording control inputs of the blocks 15, 17 and 34 (for recording units in blocks 17 and 34), to the input +1 of the counter 31 and to the And 24 element , the sign of KI is through the And 23 element and the OR 21 element to the control input of the multiplexer 16 and the inputs of the second memory block 17 and the third memory block 3 controlling the recording of zero.

When the sign NI'v appears at the output of the buffer register 11, the first memory block at the address, which is the number. the source of information that has started to work, the reading of the counter of 13 addresses is recorded, a logical unit is written to the third memory block 34 at the address of the received source, meaning that this source is taken by the device for processing, and the unit that appears at the output of the third memory block 34 allows the zone number to be decrypted by the decoder

14, at the control input of which there is also a resolving logic unit with the inverse output of the second memory block 17. The signal from the output of the decoder 14 enters the corresponding key 18 and opens it for the information part from the buffer register 11 to pass into the free zone of the drive 1. In addition, the NI flag writes to the second block 17 of the memory of the logical unit, which means that the zone with this data. The address in drive 1 is busy receiving information. Counter 31 adds one. The logical unit that appeared as a result of the output of the second memory block 17 goes to the And element 12, allowing the reference signals to pass to the address counter 13, which enumerates the addresses at the input of the second memory block 17 through the multiplexer until a logical zero appears on the other output of this block 17 blocking element And 12. The presence of logical zero in the j-th cell of the memory block, where 0 GB j _ <X means that the j-th memory zone of drive 1 is free to receive information from a new source. In the case of the start of such a source, an NI sign appears at the output of buffer register 1.1 and the described process is repeated again. Thus, as soon as new working channels appear in the first memory block 15, recording is done at addresses that are numbers of working sources, addresses of memory zones of drive 1, in which information from attached sources will accumulate (X is the number of drive memory zones -1) .

In the process, the appearance of an information word without service signs (NI, KI) from any source will cause reading from the first memory block 15, the memory zone address of drive 1, in which information from this source is accumulated, and this address will be decrypted (if there is one from the output of the third memory block 34) and the inclusion of the corresponding key 18.

If the source of information ends, the indicator KI appears at the output of the buffer register 11, which arrives at the control input of the multiplexer 16 through the OR element 21 and connects the output of the first memory block 15 to the address input of the second memory block 17, in addition, the sign of the KI is sent to the control entries the zero inputs of the second memory block 17 and the third memory block 34, as well as to the control input -1 of the counter 31. Thus, at the address, which is the address of the memory zone of drive 1, which received information from this source in watts The second memory block 17, a logical zero is recorded, which means the freeing of this memory zone of the drive 1 for receiving information from another source, a logical zero at the address of the information source in the third memory block 34 means the removal of this information source from processing, the number of occupied memory zones of the drive 1 is reduced by unit (in counter 31). Occupation of the vacated zone will be carried out after setting the address of this zone on the counter 13 and the appearance of the service sign NI at the output of the buffer register 11.

The presence of a unit at one of the outputs of the decoder 14 puts the counter 8 in a direct count state and changes its state. The same signal opens the key 18 and the information is copied to the memory zone of the drive 1, assigned to this information source.

Single impulse generators 10 are connected to the inputs of the memory zones of drive 1, which generate a signal when one data block is transferred from the corresponding memory zone of drive 1. These signals are sent to the corresponding counters of 8 states.

In the presence of a signal from the generator 10 and the deciding unit 9 of one information channel, the counter 8, assigned to this information channel 15, operates in the mode of counting down. When one of the counters 8 of the states is set to zero, the corresponding decision block 9 puts the corresponding output key 7 in the closed state and puts the output distributor 2 into the next state, which determines the output of information from the next memory zone of the drive 1.

The counter 31 operates on incoming at its inputs service, signs of NI and KI. If the number of input working sources exceeds the number of memory zones of drive 1 3Q (i.e., counter 31 sets a certain threshold X equal to the number of memory zones of drive 1), a logic zero is set at the output of counter 31, which prohibits the passage of NI signs to control the operation of the device.

Upon receipt of information from the buffer register 11 without the NI attribute (i.e., this is information from one of the sources that have already been put into processing), its processing will be carried out similarly to that described.

Upon receipt of unnecessary information with the service tag NI address ^ 5 switching device performs its processing by priority.

The address of the incoming information channel reads the priority sign of this source in the 50 first memory block 15. If it is absent, the excess information received is not processed by the address switching device, i.e. for this information channel, the memory zone in drive 1 is not allocated and address decryption by a signal (logical zero) s is prohibited. the output of the third block 34 of the memory. When . the presence of the priority sign of this information source (the presence of a logical unit at the second output of the memory block 15) through element And 2, the trigger 29 is cocked (the logical unit at the output is set) and a non-priority channel that works (i.e., set for processing) is searched. To do this, the logical unit at the output of the trigger 29 switches the address multiplexer 33 and the counter 22 enumerates the addresses of the memory unit 15 until a non-priority source for processing is detected. When it is detected (i.e., the presence of logical units at the output of the first memory block 15 and the output of the third memory block 34, and, therefore, at the output of AND element 28), the number of the zone allocated for this non-priority channel is recorded in parallel in counter 13, the pulse shaper 30 is started and the state counter 8 is reset, and the feature, the employment of this zone in the second memory block 17, and the processing flag of the detected non-priority source are erased (zeroed).

The pulse from the output of the shaper zeroing the trigger 29 and reducing the counter by one.

Thus, the contents of the counter 31 becomes less than a predetermined threshold X, and a logical unit appears at the first output of the counter 31, allowing the passage of the sign of NI. Further, the processing of input information (i.e., priority channel information) is carried out as described previously, i.e. this channel is occupied by the freed memory zone of drive 1.

Thus, upon receipt of the amount of input information, · pre. exceeding the number of memory zones of drive 1, the address-switching device for a priority source performs the following operations: search for any non-priority channel of information processed by the device;

rewriting its zone number for the incoming priority channel;

releasing the detected non-priority channel from processing, setting the input priority channel to processing.

Claims (1)

Claim An address-switching device containing a drive, an output distributor, a block of reference frequency signals, an input distributor, a buffer register, an address counter, a first decoder, a first memory block, a multiplexer, a second memory block, five AND elements, three OR elements, and the number of occupied zones counter memory of the drive, and in each switched channel there are series-connected input register and input key, output key, state counter, decision block, memory key and single pulse generator, while controlling the input key stroke is connected to the corresponding output of the input distributor, the input of which is connected to the output of the reference frequency signal block and the first input of the first AND element, the output of which is connected to the counting input of the address counter, the output of which is connected to the first input of the multiplexer, the output of which is connected to the address input of the second a memory block, the direct output of which is connected to the second input of the first AND element, the output of the input key is connected to the corresponding input of the buffer register, the information output of which is connected with the information input of the memory key, the control input of which is connected to the input of the direct count of the state counter and the corresponding output of the first decoder, the information input of which is connected to the second input of the multiplexer and the first direct output of the first memory block, the output of the memory key is connected to the corresponding information input of the drive, output which is connected to the inputs of the output key and the single pulse generator, the output of which is connected to the information input of the state counter, the output of which through controlling unit connected to the control inputs of output switch and the counter states, the second output deciding unit is connected to the output of the distributor input, the corresponding output is connected to the second input of the decision block, the second output buffer register via series connected second element · ² cops and the first OR element connected with the first input of the counter of the number of occupied zones of the memory of the drive, the direct output of which is connected to the first input of the third element And, the inverse output of the counter of the number of occupied zones of the memory of the drive The device is connected to the first input of the fourth element And, the second input of which is connected to the first input of the fifth element And and is connected to the third output of the buffer register, characterized in that, in order to avoid loss of information from priority sources during switching, the sixth and seventh elements of Y are introduced, address enumeration counter, address multiplexer, trigger, pulse shaper, a second decryptor and a third memory block, while the inverse output of the third memory block through the sixth element And connected in series, the second element nt OR, the address enumeration counter is connected to the first input of the address multiplexer, the second input of which is connected to the fourth output 25 of the buffer register, the output of the address multiplexer is connected to the address inputs of the first and third memory blocks, the direct output of which is connected to the first input of the seventh elec βθ ment And, the second input of the second element And and the first control input of the first decoder, the second control input of which is connected to the inverse output of the second memory block, the information input of the first ^ 5 decoder ene with information. the input of the second decoder, the output of which is connected to the zeroing input of the state counter, the control input of the second decoder is connected to the first input of the third element ILI, the output of the seventh element AND, the input of the pulse shaper and the control input of the recording of the address counter, the information input of which is connected to the first direct output of the first a memory unit, the second direct output of which is connected to the second input of the second OR element and the second input of the third AND element, the third input of which is connected to the second inputs of the count the number of occupied memory zones of the drive and, the fourth AND element, the output of which is connected to the control record 1. inputs of the first, second and third memory blocks, the output of the second AND element is also connected to the second input of the third OR element, the output of which is connected to the control record 0 inputs of the second and the third memory blocks and the control input of the multiplexer, the inverse output of the first memory block is connected to the second input of the sixth element And the second input of the seventh element And, the third input of which is connected to the output of the trigger and second m the input of the fifth element And, the output of which is connected to the control input of the address multiplexer, the output of the pulse shaper is connected to the second input of the first OR element and the first input of the trigger, the second input of which is connected to the output of the third element And, and the output of the address counter is connected to the information input of the first block memory.