SU1584116A1 - Receiver of signals with frequency manipulation - Google Patents

Abstract

This invention relates to radio and can be used in receiving systems in the presence of intentional interference. The purpose of the invention is to increase the loyalty of the received information. To achieve this goal, the first 7 and second 8 pulse shapers, the second decoder 9, the clock synchronization unit 10, the frequency divider 11 and the comparison unit 12 are entered into the receiver. The clock synchronization unit 10 is controlled by the signal of the subtractor 6, and the limits of the code combinations of the pressed signal are determined using a frequency divider 11. In comparison unit 12, an analysis of the combinations decoded by the first 5 and second 9 decoders is performed. If the received combinations are not mutually inverse, then a decision is made about the presence of errors in the received signal, and no information is given to the recipient. 1 il.

Description

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This invention relates to radio and can be used in receiving systems in the presence of intentional interference.

The purpose of the invention is to increase the accuracy of the received information.

The drawing shows a structural electrical circuit of the receiver of signals with frequency shift keying.

The frequency-controlled signal receiver contains the first band-pass filter 1, the first quadratic detector 2, the second band-pass filter 3, the second quadratic detector 4, the first decoder 5 and the subtractor 6, as well as the first 7 and second 8 pulse drivers, the second decoder 9, block 10 clock synchronization, frequency divider 11 and comparison block 12.

The receiver of signals with frequency manipulation works as follows.

The received signal in the form of single and zero parcels with possible interference enters the inputs of the first 1 and second 3-band filters. The first 2 and second 4 quadratic detectors pick out the envelopes of the received signal In the subtractor 6, a signal is generated that synchronizes the operation of the clock synchronization unit 10. Simultaneously, the first 7 and second 8 pulse formers from the received envelopes under the action of the clock sequence produce binary signals. In the event that the received parcel corresponds to a single one, then a single signal appears at the output of the first former of 7 pulses, and a zero signal appears at the output of the second driver of the 8 pulses. When receiving a zero send, the values of the signals are reversed. Since the transmitting side can radiate either a zero or only a single parcel to each clock cycle, in the absence of interference ia the inputs of the first 5 and second 9 decoders act inversely to each other. In this connection, when receiving, for example, a combination consisting of only single parcels, the second decoder 9 should decode the first decoder 5 with the combination of zero parcels. The boundaries of the code combinations are determined using a frequency divider 11, synchronized by a signal from the second output of the second decoder 9.

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terminations of code combinations by the signal from the output of the frequency divider 11; analysis of the combinations decoded by the first 5 and second 9 decoders is performed. If these combinations are inverse, the corresponding signal is given to the recipient, if this condition is not met, then a decision is made about the presence of an error.

In the proposed receiver, in comparison with the known one, the fidelity of signal reception is significantly increased by increasing the number of detected errors, especially under conditions of deliberate harmonic or impulse noise.

Claims (1)

The invention is a frequency-controlled signal receiver comprising a series-connected first bandpass filter and a first quadratic detector, a second band-pass filter and a second quadratic detector, the first decoder and subtractor, the outputs of which are connected to the outputs of the first and second quadratic detectors, the inputs of the first and second The second bandpass filter is an input to the receiver, characterized in that, in order to improve the accuracy of the received information, the first and second forms are introduced pulse generators, second decoder, clock synchronization unit, frequency divider and comparison unit, the first, second and third inputs of which are connected respectively to the output of the first decoder, the output of the frequency divider and to the first output of the second decoder, the first input and the second output of which are connected respectively to the output the first pulse shaper and the first input of the frequency divider, the second input of which, the second input of the second decoder and the first input of the first decoder are connected to the output of the clock synchronization unit, the input of which is The subtractor output is connected, the output of the second quadratic detector is connected to the second input of the first decoder through the second pulse shaper, the output of the first quadratic detector is connected to the input of the first pulse shaper, and the output of the comparison unit is the output of the receiver.