SU1584086A1 - Synchronous filter - Google Patents

Abstract

This invention relates to electrical measuring technology. The purpose of the invention is to reduce the interference power. The synchronous filter contains an algebraic adder 1, a key 2, a clock Mr. 3, a resistor 4, a switch 5, an adder 6, capacitors (K) 7 and 8, an integrator 9 and an amplifier 10. A switch 5 periodically connects K 7 and 8 through resistor 4 to input voltage, charge them. In order for the pulse on the carrier pulses not to participate in the charge of K 7 and 8, the key 2 during the pause between the pulses disconnects both integrating circuits (resistor 4 and K 7, resistor 4 K8) from the input signal. The alternating current voltages of K 7 and 8 are algebraically summed in summer 6. The resulting voltage of the additive noise is transformed according to the proportional-integral law with the help of the integrator 9 and the amplifier 10. The output of the filter decreases dramatically. In order to increase the suppression, the RF interference is selected from a predetermined ratio of the integration time constant of both integrating circuits. The goal is achieved by suppressing low frequency interference and high frequency interference, eliminating the influence of the high frequency "outlier" of the pulse signal, as well as the constant component present in the input signal. 2 Il.

Description

31584086

The invention relates to electrical measuring equipment and can be used in frequency selection devices operating with low levels of useful signals.

The purpose of the invention is to reduce the interference power.

Different current voltages

FIG. 1 shows the electrical block diagram of the synchronous filter | 0 on the first 7 and second 8 capacitors pa; in fig. 2 are timing diagrams that are algebraically summed to a summation of the operation of a synchronous filter.

The synchronous filter contains algebraic adder 1, key 2, clock generator 3, resistor 4, switch 5, adder 6, first end 15

additive low-frequency noise and its voltage at the output of the synchronous filter decreases sharply (Fig. 2d). Thus, the signal at the output of the gate 6, with the result of the summation is the voltage of the additive noise. This voltage is transformed according to the proportional-integral law using parallel-on-capacitor 7, second capacitor 8, other integrator 9 and amplifier 10, and tegrator 9, amplifier 10, subtracted in algebraic summat. The synchronous filter operates the next Pe 1 from the input signal. Closes. 20 Negative feedback loop

The signal of the rectangular carrier, modulated by the parameter being measured, is fed to the summing input of the algebraic adder 1. This signal in general is an ad-bode from all three types of interference f, (t), a simple mixture of useful signal and and $$ (f). For the measured sigme (Fig. 2a) of the tail (carrier envelope) and high-resistivity + $ /) + Wt) + 3 (t), the frequency disturbance $ t (t) is the transfer where iiz / c is the square signal carrier; 30 „(t) .- low-frequency noise (ten hertz);

$ 4 (t) - high-frequency noise (ten kilohertz);

Ј5 (t) is the emission on carrier pulses due to transients in the measuring path and, in part, the function of the synchronous filter is determined by the expression

.

Where

R is the resistance of the resistor 4; C - capacitor capacitance 7 or 8;

For low frequency interference пом, (t) (up to hundreds of hertz), the transfer function 40 has the form:

in line with

sensor.

In steady state, as a result of the periodic connection of the first 7 and second 8 capacitors using switch 5 through a resistor

For low frequency interference пом, (t) (up to hundreds of hertz), the transfer function 40 has the form:

W | i (p) -m-

Vvt T2K p2 + 2ЈT „p + G where;

4 TU GGR

4 to the input voltage, they charge d5 5 IT of the coefficient of damping to some established 4 current values. A separate integration circuit is formed for the positive pulse envelope (resistor 4, first capacitor 7) and an JQ integrating circuit for negative pulse envelope (resistor 4, second capacitor 8). The constant times of these chains are chosen in such a way that

do not distort the useful information, peg, you can achieve the maximum editable carrier envelope. So that-

The second generator 3 controls the operation of the key 2, during the pause between pulses (Fig. 26, c) it disables both of the two; K - gain factor

amplifier 10;

T is the integrator integration time constant 9. Change the gain factor K, and

T, attitude is independent of each other.

Noise interference $, (t) in a given frequency range.

To increase the suppression of high-frequency interference, the magnitude of T should

tagging circuits from the input signal. The duration of the pause is calculated in advance so that the ejection on the carrier pulses does not participate in the charge of the first 7 and second 8 capacitors. For this, it is usually sufficient to select a pause duration of 20-30 microseconds.

Different current voltages

on the first 7 and second 8 capacitors are algebraically summed in the summation

additive low-frequency noise and its voltage at the output of the synchronous filter decreases sharply (Fig. 2d). Thus, the output signal is free of all three types of interference f, (t), and $$ (f). For the measured signal (carrier envelope) and high-frequency noise $ t (t), the transmission

boden from all three kinds of interferences f, (t), and $$ (f). For the measured signal (carrier envelope) and high-frequency noise $ t (t), the transmission

the synchronous filter function is defined by

.

Where

R is the resistance of the resistor 4; C - capacitor capacitance 7 or 8;

For low-frequency interference Ј, (t) (up to hundreds of hertz), the transfer function is:

W | i (p) -m-

Vvt T2K p2 + 2ЈT „p + G where;

Ј IT coefficient of damping- 4 nio--

neither; K - gain factor

amplifier 10;

T is the integrator integration time constant 9. Change the gain factor K, and

T, relation - independently of each other

ha, you can achieve maximum

Noise interference $, (t) in a given frequency range.

To increase the suppression of high-frequency interference, the magnitude of T should

S

AT

P

n n n

Claims (1)

A synchronous filter containing a resistor, first and second capacitors, the first conclusions of which are connected, and the second conclusions are connected respectively to the first and second outputs of the switch and to the inputs of the adder, the second output of the resistor is the output of the synchronous filter, a clock generator, the first output of which is connected to the control input a switch, characterized in that, in order to reduce the interference power, an integrator, an amplifier, an algebraic input adder, a key, an algebraic input adder output are connected to an input ohm of the key, and the subtracting input - with the outputs of the integrator and amplifier, the inputs of which are connected to the output of the adder, and the output of the key is connected to the first output of the resistor, the second output of which is connected to the input of the switch, the control input of the key is connected to the second t output of the clock generator, the first conclusions capacitors connected to a common bus.