SU1580557A1 - Wide band logarithmic analog-digital converter - Google Patents

Abstract

The invention relates to a measurement technique and can be used in various devices (including selective with frequency conversion) semi-automatic and automatic measurement and tolerance control of amplitude-frequency characteristics levels on a logarithmic scale in a wide dynamic range of levels with small error and high resolution. The invention allows the dynamic range to be expanded, the resolution to be enhanced, and the applications expanded. This is achieved in that the converter containing measuring amplifier 1, rectifier 4, narrow-band logarithmic analog-to-digital converter 5, comparators 6-10, block 20 of reference voltages, control unit 11, has an adjustable attenuator 3, converter 13 of code, totalizers 14 and 15, registers 16 and 17, block 18 synchronization. 3 hp f-ly, 8 ill., 1 tab.

Description

ъ

1

and

sync

315

The invention relates to a measurement technique and can be used in various devices (including selective ones, with frequency conversion) of semi-automatic and automatic measurement and tolerance control of levels, attenuation, amplitude-frequency characteristics on a logarithmic scale in a wide dynamic range of levels with small error and high resolution.

The aim of the invention is to expand the dynamic range, increase the resolution and expand the scope.

Figure 1 shows the functional diagram of the proposed Converter; figure 2 - timing diagrams of the Converter; FIG. 3 is a functional diagram of a synchronization unit; 4 is a functional block diagram of the control unit; FIG. 3 shows timing diagrams of operation of the control and synchronization blocks; figure 6 is a functional diagram of the measuring amplifier; figure 7 - timing diagrams of transients in an adjustable attenuator; FIG. -8 is a family of diagrams explaining the movement of the transducer in certain coordinates.

The wide-range logarithmic analog-to-digital converter (figure 1) contains measuring amplifier 1, input bus 2, adjustable attenuator 3, rectifier 4, narrow-band logarithmic analog-digital converter 5 (ULARP) comparators 6-10, control unit 11, inputs 1 2 converters 1 3 codes, adders 14 and 15, registers 1 6 and 17, synchronization unit 18, bus 19 Setting well

l, block 20 of reference voltages and output 21.

In Fig.2, diagram 22 depicts the pulses of the synchronization frequency arriving at the first input of block 18, diagram 23 — pulses arriving from the first output of block 18 to the input of sync45.

The control unit (Fig. 4) contains the third information input 45, the first installation input 46, the clock input 47, the first 48 and the second 49 information inputs, triggers 50.1 and 50.2. elements And 51.1. 51.2, 51.3 shaper 52 short pulse inverter 53, elements OR NOT 54.1 and 54.2, counter 55, element AND 56, code limiting unit containing digital comparators 57 and 58, first outputs 59, fourth 60 and fifth fifth information inputs, second input 6 Installation, inverter 63, EXCLUSIVE element OR 64, element OR 65, trigger 66, clock generator 67, element AND 68, code restriction unit containing digital comparators 69 and 70, counter 71, second outputs 72.

5, diagram 73 depicts

ULACP 5, the diagram 24 - im- signal at the output of the divider 31, diagrams from the second output of block 18 to the clock input of the block 1 1, diagram 25 - write pulse coming from the third output of the block 18 to the input of the register entry 16, chart 26 - write pulses arriving from the fourth output of block 18 to the input of register register 17, diagram 27 — pulse Setting zero, arriving 55

frame .74 is the signal at the inverse output of the trigger 33, chart 75 is the signal at the output of the inverter 32, chart 76 is the signal at the output of the divider 34, diagrams 73 and 76 (figure 5) are given for n 10, n 2, where nf and n2, the division factors of frequency dividers 31 and 34 (it is assumed that dividers 31 and 34 operate according to

0

five

0

five

0

35

40

45

From bus 19 Setting zero to second input of block 18, diagram 28 — impulse Setting coming from first output of block 18 la first and second inputs Setting block 11. Time points: T1 - leading edge, T2 - falling edge of impulse Setting zero, TZ is the leading edge, T5 is the leading edge of the pulse Setting, T4 is the moment of the first (when setting zero) switching the gain of the measuring amplifier 1, T5 is also the beginning of tuning the adjustable attenuator 3, T6 is ending the tuning of the adjustable attenuator 3, T7 is the ending of transients Sov, T7 to T8 - one clock cycle of the ULAPP conversion 5, T8 - write the result to register 16 (Fig. 1). Ending the zero setting mode.

The synchronization unit 18 (FIG. 3) contains the first 29 and second 30 inputs of the block, the frequency divider 31, the inverter 32, the trigger 33, the frequency divider 34, the trigger 35, the first 36 and the second 37 dividers with the decoder, And 38 and 39 elements, outputs 40-44 synchronization unit.

The control unit (Fig. 4) contains the third information input 45, the first installation input 46, the clock input 47, the first 48 and the second 49 information inputs, triggers 50.1 and 50.2. elements And 51.1. 51.2, 51.3, short pulse shaper 52, inverter 53, elements OR NOT 54.1 and 54.2, counter 55, element 56, code limiting unit containing digital comparators 57 and 58, first outputs 59, fourth 60 and fifth fifth information inputs , second input 62 Installation, inverter 63, element EXCLUSIVE OR 64, element OR 65, trigger 66, clock generator 67, element AND 68, code limiting unit containing digital comparators 69 and 70, counter 71, second outputs.

5, diagram 73 depicts

five

frame .74 is the signal at the inverse output of the trigger 33, chart 75 is the signal at the output of the inverter 32, chart 76 is the signal at the output of the divider 34, charts 73 and 76 (figure 5) are given for cases n 10, n 2, where nf and n2, the division factors of the frequency dividers 31 and 34 (in this case, it is assumed that the dividers 31 and 34 work in a positive manner); diagram 77 - signal at the inverse output of the trigger 35; diagram 78 is a signal, at the second output of counter 36, diagram 79 is a signal at the direct output of flip-flop 66, diagram 80 is the counting interval of counter 71; diagram 81 is the signal at the direct output of the trigger 50.1, diagram 82 is the diagram at the direct output of the trigger 50.2. The designations of the diagrams 22-28 and the times T1-T8 (Fig.5) are the same as in Fig.2.

The measuring amplifier (Fig. 6) contains analog input 83,. &Amp; control 84, bus 84.1-84.6 control of amplifier stages, filter 85.1, first amplifier stage 86.1 contains analog multiplexers 87.1 and 87.2, and amplifier (with fixed gain) 88.1, the subsequent amplifier stages 86.2-86.6 contain, respectively, controlled amplifiers 88.2-88.6 and filters 85.2-85.6, the analog output of the measuring amplifier is output 89. The control of the amplifier stages 86.2-86.6 is carried out by switching using analog switches 6 are not shown) on control buses 84.1- 84.6, the signals on which are determined by the Ng code at the control input 84 and the decoder 90.

The wide-range logarithmic analog-to-digital converter (FIG.) Works as follows.

Measuring amplifier 1, the gain of which can take discrete values with step L and (dB) depending on the output code of block 11, is feedback-linked through blocks 3,, 7 and 1. The stationary condition of this system4 performs the analysis of block 11 generating code N is a condition

i01 un io5,

(D

where U is the input voltage ULACP 5, which has a range (zone) of exact logarithm

2018

U

05

(2)

U01, Ufl5.- the first and fifth reference voltages coming respectively from the first and second outputs of block 20.

0

five

0

five

0

five

0

five

0

five

Condition (I) is the inverse of the disjunction of logical functions.

F, - and (and; performed by comparators 6 and 7, respectively. If the condition (1) is not fulfilled, block 11 increases or decreases the N code by one in one direction or the other until condition (1) is not met. coarse logarithmization of the input voltage of the transducer is performed with a resolution determined by the quantization step L of the gain of the measuring amplifier I, and the result of coarse logarithmization is reflected by the code value N. whose low-order weight is L. Ng code change occurs in discrete time, defined by the edges of pulses being repetition rate, arriving at the clock input of block 11 (Figure 2, figure 24).

When condition (1) is fulfilled, the voltage of the Un ULAPP 5 is converted to the Nn code with a resolution tf (dB) equal to the low-order weight of the converter 5 (Fig. 1).

Codes N p and N l are fed to the adder 14: Mn - directly, a Ng - through the converter 13 (its output code N pmo), so that the output code of the first adder 14

Nc N n + N Nn + n-N, (3) where n is the conversion factor of block 13, which, to ensure equality of the weights of the lower bits of the N codes

p -5L

i

and Nn must satisfy the relation

Thus, expression (3) is the result of the logarithm of the input voltage of the converter, and the dynamic range is determined by the measuring amplifier, and the resolution is within the limits of Dn (2) ULACP 5.

The ratio between the range D n of the converter 5 and the quantization step L of amplifier 1 is selected

.(four)

This allows you to view1 with high resolution, without switching the amplifier, a range of dynamic range

U -, - from any chosen level.

In addition, expression (4) also guarantees (along with the sampling of the switching times of amplifier 1) stability, since after any switching of amplifier 1, the operating point falls within the range of Dn. and will stand

to ensure that conditions (6) are possible at any input level.

The zero setting is carried out by phase shift.

The first phase is the time interval (T1, TA). After arriving at the bus 19 Setting the zero pulse for the duration of any edge of it at least at all-Tg-T1 (figure 2, diagram 27),

L person

and

In register 16, an N4fl shoe can be written corresponding to any selected level at the input of the converter. In this case, the output code of the converter $ at the fifth output of block 18 is formed (after subtracting in the adder 15) the pulse setting (figure 2, the duration and position on the time axis relative to the synchronization frequency pulses (figure 2, chart 22) can be arbitrary,

N

NC- "with

(5) ma 28), the fronts of which are rigidly connected to the pulse sequence 24 (figure 2 and which goes to the inputs

is centered and improves the usability of the transducer when measuring the amplitude-frequency setting of the unit 11} figure 1). characteristics. At the time of the TZ, the front of the pulse 28 (FIG. 2), the converter, is provided for, the measuring mode and block 11 are prepared for the possible setting mode. Zero gain of the measurement gains In the measurement mode at the outputs of the amplifier 25. At the time of TK ka 18, pulsed signals operate, block 11 establishes fixed diagrams of which are shown in Fig. 2 (up to time point T1). Pulses 23 (Fig. 2) synchronize ULACP 5 (Fig. 1), the time position of these signals is 30 and 4 and install with the output voltage - pulses corresponding to the completion pre- voltage comparator 8 performs lo- guide formation, for example, the recording function of the results based communities in that the transducer register 5, the pulses 24 (Figure 2) determining the gain switching moments

transfer coefficient K p0 of block 3. From-time TK until T4 ends transients of block 3

35

F3 F3 (Un Ufl4). (9) If by the time T4 F 0, then the attenuator 3 (FIG. 1) is rebuilt to

fulfillment of condition (6), starting from T5 to Tb. If by the time T4 PZ 1, then this means that the voltage Un is too low, so much so that the adjustable attenuator 3 is not able to increase it until the condition (6) is met.

measuring amplifier 1, pulses 26 of information from the output of adder 15 (Fig. 1) is written into register 17.

In the zero setting mode (the input level of the converter should be constant), the attenuation coefficient / transfer coefficient 3 is automatically adjusted so that when the installation is completed, the input voltage of the ULATS 5 is within a sufficiently narrow interval.

 wooi 6 where U U03 are the thresholds for the comparators 9 and 10, respectively.

These comparators perform logical functions.

F4 (Un 7 Uoa), Fs (). (7)

The range of adjustment of the adjustable attenuator 3 must be

D

(eight}

to ensure that conditions (6) are possible at any input level.

The zero setting is carried out by phase shift.

The first phase is the time interval (T1, TA). After arriving at the bus 19 Setting the zero pulse for the duration of the fifth output of the block 18, a pulse is formed (figure 2, diagram and its position on the time axis relative to the synchronization frequency pulses (figure 2, chart 22) can be arbitrary,

of the amplifier 1. At the time of the TZ, the block 11 establishes a fixed and 4 and sets the output voltage of the comparator 8, performing a logical function

transfer coefficient K p0 of block 3. From-time TK until T4 ends transients of block 3

of the amplifier 1. At the time of the TZ, the block 11 establishes a fixed and 4 and sets the output voltage of the comparator 8, performing a logical function

F3 F3 (Un Ufl4). (9) If by the time T4 F 0, then the attenuator 3 (FIG. 1) is rebuilt to

fulfillment of condition (6), starting from T5 to Tb. If by the time T4 PZ 1, then this means that the voltage Un is too low, so much so that the adjustable attenuator 3 is not able to increase it until the condition (6) is met.

The second phase T4-T5. In this case, the block 11 at the time T4 increases the gain of the amplifier 1 at an about the bottom level.

Third phase. At time T5-T6, the attenuator 3 is rebuilt. By the time T7, the transients in amplifier 1, attenuator 3 and rectifier 4 are finished.

Fourth phase. Until T8, ULACP 5 logs new IL values. At the time T8, a single pulse 25 is received from the fourth output of block 18 to the input of the register entry 17 (figure 2), after which the output code of the converter according to expression (5) is zero. With subsequent changes in input voltage

The transducer reads the result from the level recorded at zero setting.

During the zeroing mode, for the mode from time T) to time T8 (FIG. 2), the write pulses to register 17 from the fourth output of synchronization unit 18 do not come to prevent the information (f.chg, 2 and 5) from writing information to register 17. - Element 38 extracts from the sequence formed at the first output of divider 36, one pulse arriving at the output 42 at the input of the register entry 16 (Figures 2 and 5, diagram 25).

Block 1 (figure 4) works as follows

transform-) 0 way.

their transitional T8 coefficient of 3 remains as follows (

The range of the limits of the braid is high

Dn m + -g- to

™ 4

20

(Y) (y

25

The code N of the block with which the signal dt by the signal in the input de resolves the right of the reverse, zero. Og counter rators 5 Directional scrap is sent to either the input 47 in the mode and mi 54.1 and in the input mode 45 hera 50.

by extension

  D, + Dt. (12)

This is particularly important, for example, when measuring the frequency response, in particular, of filters, when it is necessary to measure any part of the frequency response with the maximum resolution and minimum error.

The synchronization unit 18 (FIG. 1) operates as follows.

The divider 36 (FIG. 3) generates at its outputs pulses with a duration determined by the synchronization frequency period fCMKXp (input 29) and the repetition period determined by the division factor nf divider 31 (the diagrams are given for 10). The operation of the divider controls the trigger 33. The presence of an inverter leads to an advance of the leading edge of the pulse 28 of the leading edge of the pulse 24 (Figures 2 and 5).

The divider 37 generates a pulse 28 at the output 44 (Figures 2 and 5) An installation whose duration is determined by the division factors n of the divider 31 and n of the divider 34 (diagrams are given for n 2), and the edges of the pulse 28 are tied to the sequence 24 (Fig .2 and.5).

Element 39 at the signal with trigger 30

35

40

45

50

55

The NJ code is removed at block 59 output from counter 55. It is assumed that the counter is controlled by the following signals: code changes occur on the basis of positive differences at such a input and logical 1 m at the resolution input, increase in the code occurs at a logical unit at the reverse input, reduction - with a logical zero. The possible counter states are limited by digital comparators 57 and 58 and elements 51.2 and 51. The counting direction is generated by the signal from input 48. The switching times are determined by the edges of the pulses from input 47. The resolution to the account (logic 1 at the resolution input) in the measurement mode elements 54.1 and 54.2 are formed from inputs 48 and 49, and in the zero-setting mode, also from input 45 by element 51.1 via triggers 50.1 and 50.2.

The code is removed from the output of counter 7. Permission to counting the p of a logical unit is formed by trigger 66 (Figure 5, diagram 79). The inclusion of three heras 66 occurs at the moment of the TOR (Fig. 5) along the leading edge of the pulse 28 (Fig. 2 and 5), the trigger 66 is turned off through the elements 63-65 upon reaching the voltage Un. zones (6) by commands from inputs 60 and 61 or through elements 56, 68, 65,69 and 70 if the code takes one of the boundary allowable values analyzed by digital comparators 69 and 70. The count direction is determined by the signal from input 60 through inverter 63 (with logical unit at the output of the inverter co increases). The tuning rate depends on the frequency of the generator 67. Setting a fixed transfer coefficient of the attenuator 3 occurs on a pulse 28 Setting (Figures 2 and 5) from the input 62.

Measuring amplifier (6) works as follows.

The switching of the amplifier Qasr 35 stops the supply of the pulses 26 to the kada 86.1 by analog

) 0 way.

 (

0

five

0

five

0

five

0

five

The NJ code is removed at block 59 from counter 55. It is assumed that the counter is controlled by the following signals: code changes occur by positive drops at the clock input and logical 1m at the resolution input, code increases at a logical one at the reverse input, decrease at logical zero The possible counter states are limited by digital comparators 57 and 58 and elements 51.2 and 51.3. The counting direction is generated by a signal from input 48. Switching moments are determined by the pulse edges from input 47. The counting resolution (logical 1 at the resolution input) in the measurement mode is formed by elements 54.1 and 54.2 from inputs 48 and 49, and in setting mode zero also from the input 45 element 51.1 through triggers 50.1 and 50.2.

The code is removed from the output of the counter 71. The permission to account p as a logical unit is formed by the trigger 66 (Fig. 5, Chart 79). The trigger 66 is turned on at the moment of the TOR (FIG. 5) on the leading edge of the pulse 28 (FIGS. 2 and 5), the trigger 66 is turned off through the elements 63-65 upon reaching the voltage Un. zones (6) by commands from inputs 60 and 61 or through elements 56, 68, 65,69 and 70, if the code takes one of the boundary acceptable values analyzed by digital comparators 69 and 70. The count direction is determined by the signal from input 60 through inverter 63 (with logical unit at the output of the inverter increases the code). The tuning rate depends on the frequency of the generator 67. Setting a fixed transfer coefficient of the attenuator 3 occurs on a pulse 28 Setting (Figures 2 and 5) from the input 62.

Measuring amplifier (6) works as follows.

Switching amplifier kpP15

multiplexers 87.1 and 87.2, while at high levels of the input signal, the amplifier 88.1 of the amplifier path is turned off. The structure of FIG. 6 allows the measurement amplifier to be performed both in the radio frequency version and in the form of a DC amplifier. In the first of these, the filters are made bandpass, the 88 J amplifier is low noise. In the second embodiment, the filters are implemented in the form of low-pass filters, the amplifier 88.1 - with a small offset (for example, with modulation by demodulation). Expansion of the converter range is provided: in the area of large levels by the use of amplifiers 88.2-88.6, which do not have a sufficiently large range, but capable of transmitting large levels, in the area of small levels by the use of low noise of the amplifier (88.5), which at large levels from the path is turned off.

Conversion error of the entire converter at low levels

further at 10. The transition is characterized by switching on the cascade 86.1 and turning off the cascade 86.5. Cascade 86.6 is controlled by the lower bit of the binary NIJ code, and the lower bit is not involved in the formation of the unitary code. Cascade

five

12

It is determined: in the radio-frequency variant, by the noise of the first stage (amplification by the stages for this purpose is unevenly distributed — the first stage has a maximum amplification); in the variant of the DC amplifier, by noise and offset of the first stage. In the known transducer, the amplification of the cascades is the same (the cascades are identical), hence the bias and noise of the first few cascades will affect the conversion error, to which more stringent requirements for both noise (displacement) and dynamic range must be made. In the proposed transducer, the requirements for the first stage are 86.1 (Fig. 6) and to the totality of the cavities 86.2-86.6, as to two separate parts, can be reduced, and as a result, the parameters of the entire amplifier are improved.

The decoder 90, which can be made on the basis of a persistent storage device, implements the following table.

It is more or less optimal in view of the requirements for the range value, the number of cascades at a given magnitude of the gain step.

Until the moment of the TZ, the input voltage of the unit 5 is in the zone (1). At the moment of the TZ, the transfer ratio of the attenuator 3 is forcibly set

Crv 0.5, tuning range D

Kl

lies within 0.25,

those. . Increasing Dp above this value is impractical because the requirements for range amplifier 1 increase. As can be seen from figure 5, pulse 28 covers two pulses of sequence 24, the counter 55 of which is switched by pulses (figure 4 therefore, during TK and T5 J can be switched twice. Of these, the first switch (fig. T4) is assigned to return Un to zone (1), the second to transfer Un from zone (U01, U05) to zone (Ufl1, U04, i.e. the zone from which unit 3 reachesU03 + U04 is level U

HO 2 p I (Fig.7) .In the original

01

Prime

the state before zeroing U n U (section I-0).

Cr K, iits 0,25. At the same time, when installing, Kp is increased to 0.5, i.e. by 6 dB (phase 1-1). At time T4, the gain of amplifier 1 is reduced by one step on command from a comparator 6 (section 1-2).

K „Cr 0.5. Transfer coefficient

0 tf

Attenuator 3 is unchanged (region 1-3).

Cr. ::. When installed, the CR is stirred to Kr 0.5, i.e. 6 dB (section 1-4).

In all cases of Example 1, T5 Un is located in the zone reachable by the Un0 level attenuator. Example 2. U p 3-Ua4.

Consider one of the cases K p K 0.5. When installing, Kp is not measured (section 2-1).

Case Cr 1. When set, the K ' value decreases by 6 dB (section 3-1).

PRI me R 3. ,,.

K-0.5 (plot 4-0). When set, the value of Kp does not change (section 4-1).

Cr Cr icl 0.25. When set, the value of K "is increased by 6 dB (section 4-2).

Cr Cr / L0 (1 1. When set, the value of Cr decreases by 6 dB (part 4-3), Un goes out of zone (1), at time T4 there is an increase in the gain of the amplifier by one level (section 4-4 ).

In all cases of example J. by the time T9 U4 Voi

ten

 , 15

20

25

thirty

35

40 45

The trigger 50.2 (FIG. 4) changes to 1 m at time T4 (FIG. 2, chart 89) and at time T4 does not affect the operation of counter 55 (FIG. 4).

At time T9 (Figs. 7 and 5), if un Ufl4, logical VI from the output of the circuit 51.1 (Fig. 4) through the elements 54.1 and 54.2 gives resolution to counter 55 to the account (it is assumed that, on the resolution input, counter 55 counts at P0 one). In this case, if. satisfies (1) y at the input 48 - Log.O, and at the input of the reverse of the counter 55 .1, the number NQ in the counter 55 increases by one, the gain of the amplifier 1 increases by one step (Fig.7, the curves in the area 5-1 ). Since the gain level of Ly 10 dB is greater than the ratio of the Ufl4H Uo5 levels (about 8 dB), by the time T5 U falls into the reach zone of attenuator 3. From T5, by tuning the attenuator 3 Un is output to the zone U02, U0i.

Fig. 8a shows a family of diagrams explaining the motion of the system in the coordinates of the input level of block 1 - the input level of block 5 (log axes) for the case. .

In a specific embodiment, Dn 20 dB, L 10 dB is selected. The movement of the system occurs in accordance with the family of diagrams of FIG. 8, b. When switching amplifier 1, the operating point each time falls into the (logarithmic) middle of the range D..

The number of possible states of the counter 55, (FIG. 4) is determined by the range of the converter and the magnitude of the gain level.

D 130 dB

 L

10 dB

 13.

The division factor nf of the divider 31 determines the ratio of the frequencies 22 (figure 5) and the sampling frequency of the converter. In a particular embodiment, a sampling rate of 1 kHz (conversion time 1 ms) is selected. With this frequency, the ULAFC 5 outputs information and the amplifier is switched (Fig. 5, pulses 24, shown for 1 10). The division factor pg of divider J4 determines the number of pulses of sequence 24 (FIG. 5), covered by impulse 28 Installation (FIG. 5), i.e. quantity

1515

switching amplifier in the installation mode zero.

The code converter 13 in a particular embodiment multiplies the M code by 1000.

Thus, the proposed converter, in comparison with the known, has a wider dynamic range, the ability to work with radio frequency and constant voltages of any polarity, reduces the conversion error to a value determined by the measuring amplifier, and implements the resolution of a narrowband LACP at any selected point dynamic range, result count, conversion relative to any selected

level

Claims (3)

Claim 1. A wide-range logarithmic analog-to-digital converter containing a measuring amplifier, whose 25 analog input is an input bus, a rectifier, a narrow-band logarithmic analog-to-digital converter, the first and second comparators, the first inputs of 30 are combined, and the second inputs are connected to the corresponding outputs of the unit reference voltages, a control unit, characterized in that, in order to expand the dynamic range, increase the resolution and expand the field of application of account of the ability to work with bipolar radio frequency signals, an adjustable attenuator, a converter and a code reader, two adders, two registers, a synchronization unit, three comparators are entered into it, the output of the measuring amplifier is connected to the analog input of the adjustable attenuator, the output of $ 5 is connected to the rectifier input, the output of which is connected to the first inputs of the second, third, fourth and fifth comparators and to the analog one. Pa whose outputs are connected to the corresponding inputs of the second register, whose outputs are the output bus, the second inputs of the third, fourth and fifth comparators are connected respectively to the third, fourth and fifth outputs of the reference voltage block, the outputs of the first, second and third comparators are connected respectively, with the first, second and third information inputs of the control unit, the first outputs of which are connected respectively to the inputs of the code converter and the control inputs of the measuring amplifier, the output The codes of the code converter are connected respectively to the second inputs of the first adder, the outputs of the fourth and fifth comparators are connected respectively to the fourth and fifth information inputs of the control unit, the second outputs of which are connected respectively to the control inputs of the adjustable attenuator, the first input of the synchronization unit is a synchronization bus , the second input is a bus setting zero, the first output of the synchronization unit is connected to the synchronization input of a narrow-band logarithmic analog-to-digital th transducer, a second output synchronization unit connected to the clock input of control unit, third and fourth outputs coupled to write inputs of the first and second registers, a fifth output is connected to the first and second setting control unit inputs. 2. The converter according to claim 1, wherein the control unit is executed on three triggers, five AND elements, a short pulse shaper, two inverters, two OR-NOT elements, two counters, four digital comparators , clock, element OR, element EXCLUSIVE OR, the third information input of the block is the first input of the first element AND, the first input the input of the narrow-band logarithmic-5Q installation of the block is a clock in the analog-digital converter, the outputs of which are connected respectively to the first inputs of the first adder, the outputs of which are connected respectively to the first inputs of the second adder and to the corresponding code inputs of the first register, the outputs of which are connected to the corresponding the second inputs of the second accumulator of the first trigger, the information input of which is a bus of the logical unit, the clock input of the block is the clock the input of the second trigger and the counting input of the first counter; the first information input of the block is the input of the first inverter and the first inputs of the first OR-NOT element and the second AND element, the second information 16 0 5 0 5 dl and h 5 Pa whose outputs are connected to the corresponding inputs of the second register, whose outputs are the output bus, the second inputs of the third, fourth and fifth comparators are connected respectively to the third, fourth and fifth outputs of the reference voltage block, the outputs of the first, second and third comparators are connected respectively, with the first, second and third information inputs of the control unit, the first outputs of which are connected respectively to the inputs of the code converter and the control inputs of the measuring amplifier, the output The codes of the code converter are connected respectively to the second inputs of the first adder, the outputs of the fourth and fifth comparators are connected respectively to the fourth and fifth information inputs of the control unit, the second outputs of which are connected respectively to the control inputs of the adjustable attenuator, the first input of the synchronization unit is a synchronization bus , the second input is a bus setting zero, the first output of the synchronization unit is connected to the synchronization input of a narrow-band logarithmic analog-to-digital th transducer, a second output synchronization unit connected to the clock input of control unit, third and fourth outputs coupled to write inputs of the first and second registers, a fifth output is connected to the first and second setting control unit inputs. 2. The converter according to claim 1, wherein the control unit is executed on three triggers, five AND elements, a short pulse shaper, two inverters, two OR-NOT elements, two counters, four digital comparators , clock, element OR, element EXCLUSIVE OR, the third information input of the block is the first input of the first element AND, the first input the unit setup is the clock input of the first trigger, the information input of which is a logic unit bus, the clock input of the block is the clock input of the second trigger and the counting input of the first counter, the first information input of the block is the input of the first inverter and the first inputs of the first element OR NOT and the second element AND, the second information input of the block is the second input of the first element OR NOT, the inverse output of the first trigger is connected to the input of the installation in O of the second trigger, the direct output of which connected to the second input of the first element AND, the output of which is connected to the third input of the first element OR NOT, the inverse output of the second trigger is connected to its information input and through the short pulse shaper to the installation input of the first trigger, the output of the first inverter is connected to the input of the reverse of the first counter and with the first input of the third element AND, the output of the first element OR is NOT connected to the first input of the second element OR-HEj, the output of the second element AND connected to the second input of the third element OR NOT, the third output The first element AND is connected to the third input of the second element OR NOT, the output of which is connected to the resolution input of the first counter, the outputs of which are the first outputs of the block and through the first and second digital comparators are connected respectively to the second inputs of the third and second elements AND, the fourth information input unit is-- with the first inputs of the fourth element AND, the element EXCLUSIVE OR, and through the second inverter is connected to the first input of the fifth element AND and to the input of the reverse of the second counter, the fifth information input Loka is connected to the second input of the EXCLUSIVE OR element, the second input of the unit installation is connected to the clock input of the third trigger and the installation input of the second counter, the outputs of the fourth and fifth elements of AND are connected respectively to the first and second inputs of the OR element, the third input of which is connected to the output of the element EXCLUSIVE OR, and the output is connected to the installation input of the third trigger, whose information input is a bus of a logical unit, the direct output of the third trigger is connected to the resolution input of the second counter, The primary inputs of which are a fixed-code bus, the output of the clock generator is connected to the counting input of the second counter, the outputs of which are the second outputs of the block and through the third and fourth digital comparators are connected respectively to the second inputs of the fourth and sixth And elements, the second inputs of the first, The second, third, and fourth digital kokparatory are tires of the respective reference codes. 3. The converter according to claim 2, T is characterized in that the synchronization unit is made on two elements AND, two dividers with a decoder, two triggers, two frequency dividers and an inverter, the input of which is combined with the clock input of the first trigger and is connected to the output of the first frequency divider, and the output of the inverter through the second frequency divider is connected to the clock input of the first divider with a decoder, the installation input of which is combined with the first input of the first element And and connected to the direct output of the second trigger, the first output of the first divider the decoder is the fourth output of the block, the second output is connected to the first input of the second element, the second input of which is connected to the first output of the second divider with the decoder, and the output is connected to the installation input of the second trash and is the fifth output of the block, information input The second trigger is a logic unit bus, the clock input is the second input of the block, the input of the first frequency divider is combined with the clock input of the second divider with the decoder and is the first input of the block, the first and second outputs of which O are, respectively, the second and third outputs of the second divider with the decoder, the fourth output of which is connected to the second input of the first element AND, the fifth output is connected to the installation input of the first trigger O, the inverse output of which is connected to the installation input 0 of the second divider with the decoder, the information input of the first trigger is a bus of a logical unit; the output of the first element I is the third output of the block. D. The converter according to claim. 2, that the measuring amplifier is made on a filter, a decoder, six series-connected amplifier stages, the first amplifier stage is performed on two analog multiplexers and. the amplifier, the second, third, fourth, fifth and sixth amplifying stages are performed on series-connected controlled amplifier and filter, the output of the sixth amplifying filter the cascade is the output of the measuring amplifier, the analog input of which is connected via filter to the first input of the first analog multiplexer, the first output of which is connected to the first input of the second analog multiplexer, the second input of which is connected through the amplifier to the second output of the first analog multiplex JQ cop, the second whose input and the third input of the second analog multiplexer are combined and connected to the first output of the decoder, the output of the second analog multiplexer is output TJ P TZ P The first amplifying stage, the second, third, fourth, fifth and sixth inputs of the decoder are respectively connected with the first inputs of the controlled amplifiers of the second, third, fourth, fifth and sixth amplifier stages, the inputs of the decoder are the control inputs of the measuring amplifier, the second control input The amplifier is the input of the corresponding amplifier stage, except for the first one, and the output of the filter is the output of the corresponding amplifier stage, except for the first one. 75 T6 77 T8 FIG. 2 56fe P niliiiiiliiiiimiiHiiiimiiiimriiiimt and, (01) 23 ( buoW (UOSJOSB (3 (U09) Q, 2B Un.B B (on dxode block 5)