SU1580265A1 - Measuring transducer of root-mean-square value of voltage - Google Patents

Abstract

The invention relates to electrical measuring technology and can be used in accurately transforming the voltage of an arbitrary shape into a constant rms level when the environmental parameters vary within wide limits. The aim of the invention is to improve the accuracy of the rms conversion. To do this, keys 3-5 and block 13 are entered into the device. In calibration mode, keys 1,3,4 are open, and keys 2 and 5 are closed. As a result, zero levels arrive at the input of adders 7 and 8, as well as the multiplier of 10 signals. In this case, the adder 9, the resistor 15, the operational amplifier 12 and the block 13 form negative feedback, eliminating the error from the drift of the adder 9, the multiplier 10 and the amplifier 12. When switching to the measurement mode, the control commands and the logical inverter 14 switch the keys 1-5 the opposite state, and the block 13 is transferred to the storage mode, while the diode 17 and the capacitor 16 are connected to the output of the amplifier 12, and the converted signal goes through the diode 18, which through the analog inverter 11 goes to the adder 7. At steady state IU imzmereni transducer output voltage proportional to the rms value of the measured voltage. Adders 7 - 9 and the multiplier 10 signals form a universal analog multiplier 6 signals. 1 il.

Description

The invention relates to electrical measuring equipment and can be used for accurately transforming voltages of arbitrary shape into a constant with respect to the root mean square value when changing the parameters of the external medium within wide limits.

The aim of the invention is to improve the accuracy of the rms conversion.

The drawing shows a functional diagram of a rms voltage measuring transducer.

The converter contains keys 1 - 5, a universal analog multiplier 6 signals, consisting of an adder 7 - 9 and multipliers 10 signals, an analog inverter 11, an operational amplifier 12, a sampling-storage unit 13, a logical inverter 14, a resistor 15, a capacitor 16, diodes 17 and 18, the control input terminal 19, the zero bus 20, the input 21 and the output 22, and the input terminal 21 is connected to the input of the key 1, the output of which is connected to the subtracting and summing inputs of adders 7 and 8, respectively, and to the output key 2 whose input is connected to zero the bus 20, and its control input is connected to the control input terminal 19, the input of the logic inverter 14 and the control inputs of the sampling-runner 13 and the key 5, the output of which is connected to the zero bus 20, and the input is connected to the output terminal 22, subtractive input of the adder 8, the output of the key 4 and the input of the analog inverter 11, the output of which is connected to the summing input of the adder 7, the outputs of the adders 7 and 8 are connected to the corresponding inputs of the multiplier 10 signals, the output of which is connected to the first input of the adder 9, the output which is black The resistor 15 is connected to the anode of the diode 17, the first output of the capacitor 16 and the inverting input of the operational amplifier 12, the non-inverting input of which is connected to the zero bus 20, and the output is connected to the anode of the diode 18, the output of the key 3 and the input of the sampling-storage unit 13, the output of which connected to the second input of the adder 9, the cathode of the diode 17 is connected to the second output of the capacitor 16 and the input of the switch 3, the cathode of the diode 18 is connected to the input of the switch 4, control

.

The input of which is connected to the analogous inputs of switches 1 and 3 and the output of the logic inverter 14. The summing input of the adder 7 is the first input of the universal analog multiplier 6 signals, the second, third and fourth inputs of which are the subtracting input of the adder 7, the summing and subtracting The inputs of the adder 8 are respectively, the output of the adder 9 is the output of the universal analog multiplier 6 signals, the second input of the adder 9 is the correction input of the universal analog multiplier 6 signals.

The work of the converter consists of two cycles: Correction and Transformation.

The Correction cycle starts with the arrival of a control impulse on clamp 19. This leads to the closure of keys 2 and 5, to switching on the sampling-storage unit 13 in the Sampling mode and to opening the keys 1,3 and 4. At the same time, the inputs of adders 7. and 8 the potential of the zero bus 20 arrives, and the second input of the adder 9 is the output voltage of the zero correction circuit formed by series-connected resistor 15, the operational amplifier 12 and the sampling-storage unit.

After a certain period of time equal to the duration of the control pulse, the following voltage is established at the input of the sampling-storage unit 13:

U

+ e

(e + e r.) Kj ° i +

3 in e ° sVK04K

one

S & M-NCK

(one)

where e and e) (, Ku & x is the zero displacement voltage of the sampling-storage unit 13 and, accordingly, its transmission coefficient in the presence of drift voltages, ems, ems and e0c multiplier 10 signals, adder 9 and operational amplifier 12.

The transmission coefficient of the sampling-storage unit 13 is advisable to choose within) (-0.01-1, and the operational amplifier, then (1)

will simplify:

03

1T a-

H ex if h s ex

(2)

At the end of the control pulse, the keys 2 and 5 are opened, the sampling-storage unit 13 goes into the mode

5158

Storage and keys 1,3 and 4 are closed. At the same time, the voltages tuBx (t) + UBb | X (t) and, accordingly, Ubx (t) -U Bb.x (t) are fed to the inputs of the multiplier 10 signals and, accordingly, U6l ((t) is the input voltage, U6bw (t) is the output voltage in a transient mode, and the second input of the adder 9 is the voltage, jBX.

In steady state, the result is:

l-i

-KLgPihG0

from where

willow, "

where u

U

would

(3)

U

i в „is the rms input voltage; Jbtx is the output voltage in

new mode. Thus, the final result does not depend on destabilizing factors, and the preservation of the charge on the capacitor 16 makes it possible to increase its speed after the correction mode.

Claims (1)

Invention Formula - 5 10 15 20 25 Its input is connected to an output terminal, which is connected via an analog inverter to the first input of a universal analog signal multiplier, whose output is connected via a resistor to the anode of the first diode, the first capacitor output and the inverting input of an operational amplifier, the non-inverting input of which is connected to the zero bus, and the output the operational amplifier is connected to the anode of the second diode, the cathode of the first diode and the second terminal of the capacitor are combined, the control input of the second switch is connected to the control (in one terminal, which is connected via a logical inverter to the control input of the first key, characterized in that, in order to improve the accuracy of the conversion, the third, fourth, and fifth keys are additionally introduced into it, the cathode of the first diode through the third key - connected to the anode of the second diode, which through the fourth key is connected to the output clamp, and through the fifth key to the zero bus, the anode of the second diode Measuring transducer medium-JQ through the sample-storage unit is connected a non-square voltage value containing the first and second keys, the input of the first key is connected to the input terminal, and the input of the second key is with a zero bus, the outputs of both keys are combined and connected to the second and third inputs of the universal analog signal multiplier, four with correction input universal analog signal multiplier ,. the control inputs of the sampling-storage unit and the fifth key are connected to the control input of the second key, the control inputs of the third and fourth keys are connected to the control input of the first key.