SU1571577A1 - Parallel binary adder - Google Patents

Abstract

The invention relates to computing and can be used in arithmetic to sum up numbers represented in parallel binary code. The aim of the invention is to reduce hardware costs and improve the performance of the adder. This goal is achieved by the fact that each cell of a binary adder, containing two triggers, three AND elements, two OR elements, contains a third OR element with corresponding connections. 1 il.

Description

The invention relates to computing technology and can be used in arithmetic devices to add numbers represented in parallel binary code.

The aim of the invention is to reduce the hardware costs and increase the speed of the device.

The drawing shows a functional diagram of three adjacent cells of a parallel binary adder.

Cells 1 (i - 1) - 1 (i + 1) contain the first 2 (1 - 1) - 2 (1 + 1) and the second 3 (1 - I) - 3 (1 + 1) triggers, the first And 4 elements (i - 1) -4 (i + l), second 5 (i - l)

-5 (i + l) and the third 6 (i - 1) -6 (i + l), as well as the first 7 (i-1) - -7 (i + 1), the second 8 (i - 1) - 8 (i + + l) and third 9 (i - 1) - 9 (i + 1) elements OR. The adder also contains a bus 10 synchronization.

The adder will be described by the example of the work of the 1 (a - l), I (i) and 1 (i + 1) cells shown in the drawing. The first and second information inputs of each cell are supplied with the values of the corresponding bits of the components A and B, for example, bits aЈ and b are fed to the first and second inputs of the And 4 (i) element, which are the first and second information inputs of cell 1 (i), and also connected to them the first and second inputs of the second element OR 8 (i). According to the SI sync pulse coming from the synchronization bus 10 simultaneously to the C inputs of all the accumulator triggers, the triggers are set to the state corresponding to the state of their D inputs,

The inverse output of the second trigger 3% (i), which is the output of the inverse transfer q, is equal to the initial moment after the signal of the SI unit in that

SP

h

SP

1 J

If the value of the 1st bit of the hat would be one of the addends is zero.

Next, asynchronous rastranslation of the transfer and inverse transfer signals occurs. The value of the Transfer signal P is determined by the logical functions of elements 7 (i) 9 5 (i) and 6 (i) and their input signals Q, -,, 4b q; +, and P;.,: P; (Q; Л Q jt Л А 1, Ч) VteCtl Л qU Р, -)

. q {4i QCL. (Q °; z V Р, 1-,), ij de q +1 is the inverse re-us signal from cell 1 (i + l) | - cell transfer signal

1 (i - O;

respectively, the output of the first trigger

2 (i) and the direct output of the second trigger 3 (i) of the cell 1 O) after exposure to the SI signal.

If bits a and b} were equal to unity, then the state of triggers 2 (i)

si 1 "h

1 + 1 si 11

Q,, Q | Л - state

si

and 3 (i) (Q;, and Q; d) is initially equal to one, the inverse transfer q is zero, and the transfer is determined by the value q; +. If the signal q, –4 is zero, then the state of cell 1 (1) does not change until it is propagated by the signal of the inverse transfer q from the side of the accumulated digits of the adder, t, e until the signal q (not becomes equal to one. Similarly, until the state of cell 1 (1) changes, the signal q, 1 will be equal to its initial value q, 0 (for the above initial conditions) and will keep it at zero

signal P in cell 1 (i - 1) outside

si si depending on the value of C, {, (,

SI., SI.

and Р q; AQ (}., A (,) If the inverse transfer q, + from cell 1 (i + l) is equal to one, then after a time determined by the holding of the elements Й 5 li) and OR 7 (1 ) the transfer of P becomes equal to one and installs the triggers 2 (i) and 3 (i) on the R-inputs to zero, and on the S-input to the unit that trigger 3 (i + l) of the cell 1 (i + l). If the trigger 2 (i + l) is in the state I, i, 1, and the signal q {+1 is equal to one, the transfer propagates further through the elements 6 (i + O and-7 (i + O). the delay time of the operation of the indicated elements becomes equal to unity. Since, after the trig hera 3 (i) per unit inverse transfer q becomes equal to zero according to the expression (1) s and the unit transfer value P; is maintained by the unit state of the 2 (i + l), 3 (i + + 1) flip-flops through the elements 5 (i + l) and 7 (i i- 1) until this signal sets the triggers 2 (i 1) and 3 (i + 1) on the R-inputs to zero. Thus, it is not possible to install trigger 3 (i + l) in an indefinite state at the moment of equality of a unit of signals P J and P; 41, since the effect on R-input of a trigger 3 (1 + 1) by a signal P; +1 continues after the signal is removed until the triggers are established 3 (i + l) and 2 (1 + 1) to zero.

After setting the triggers

2 (i), 3 (i) to zero, the signal q is equal to one, and if cell 1 (i - l) has the condition for the occurrence of the transfer signal Q (, ", yL (Q (;, jtVp) 1, the signal P (- (at the output of the element OR 7 (i - 1) becomes equal to one

and sets the trigger 3 (1) on the S-input to the unit. Since in the previous stage of propagation of transfer and inverse transfer, the triggers 2 (1) and 3 (1) were set to zero, and the trigger 2 (i) is not set to one, the transfer from cell 1 (i - i) to cell 1 (i) further does not spread to cell 1 (1 + 1),

From the above, it follows that the transfer of Pr1 in any cell can occur in the process of summing a pair of numbers only once, because after the transfer signal P appears in accordance with the expression (0, the triggers 2 (i) and 3 (i) are set to zero, and if a transfer occurs in cell I (i), only the trigger will be set to one

3 (1).

At the end of the process of spreading the transfer in cell 1 (1), three situations are possible:

the state of both triggers 2 (i), 3 (i) is zero - if the bits of the terms a, b; were equal to zero and transfer from cell I (i - 1) to cell 1 (i) did not occur, or if transfer from cell 1 (i) took place; in cell 1 (i + 1) and there was also no transfer P,, or transfer P, led to the transfer P ,. and, as was proved above, could not arise again;

the state of the trigger 2 (i) is one, and the trigger s1 (1) is zero if the unit was equal to only one of the digits a; and b; and the transfer of P4-, did not occur;

the state of the trigger 2 (1) is zero, 3 (i) is one if in the situation of equality to zero the states of the triggers 2 (i), 3 (i) due to the zero value of the digits a; and b; or the occurrence of the transfer signal PJ after the arrival of equal to a unit bits a and bj, the transfer P was made; from cell 1 (1 - 1). The result of the summation in cell 1 (i) is bit Example 1.

A 0111

+ 0111

1110

0

five

0

S amounts; determined by the disjunction of the outputs of the triggers 2 (i) and 3 (i) on the third element OR 9 (i): S,

 v

Let us consider several examples of performing the summation of two binary numbers in the proposed device. The state of the first and second triggers of each cell is written with the third binary bits in square brackets, the state of the first cell trigger is recorded in the right bit of the pair, the state of the second trigger is in the left de. The punctual line indicates the distribution of the inverse transfer q, the continuous one means the distribution of the transfer of P.

0

oof

0

P DO

q g -; t

oo lp

q i о oo p

R and me 2,

0101

+ OOP

1000

p and m e p 3.

0101

+ 1001

1110

q q q if7t-}

00 01 01 P

 one

p p p

q q g

g -i t- -i-6-, "3rd oo on oo

Woo

about

about

about

q y ---- 1 q

 J - 1

01 01 00 П

01 01 10 oo

,one

V

0

7 A.

j The above description of the operation of the proposed adder and an example shows the conformity of the performed (summing in it the rules of binary arithmetic.

Claims (1)

Invention Formula A parallel binary adder containing one-digit summing cells, each of which contains two triggers, three AND elements, two OR elements, and the synchronization inputs of the first and second trigger are connected to the synchronization bus of the adder, the first input of the first element AND of each summing cell of the 1 connection is not the first information input of the adder, the first inputs of the second and third element I are connected to the output of the first trigger, the second input of the third element I is connected to the transfer input by a one-bit summing cell, the first and second inputs of the first element OR are connected to the output of the second and third elements AND, respectively, and the output is connected to the first installation input of the second trigger, the inverse output of which is connected to the inverse transfer output by a one-bit summing cell, the output of the second element OR is connected to the information input the first trigger, the transfer input of each one-bit summing cell, except the first, 1571577 D} oi 00 1. g five 0 five 0 0 yu oo oo V about V about  j is connected to the transfer port of the previous cell, characterized in that, in order to reduce hardware costs and speed, a third OR element is introduced into each one-bit summing cell, the first input is connected to the output of the first trigger , the second input is connected to the direct output of the second trigger and to the second input of the second element I, the third input of which is connected to the third input of the third element I and to the input of the inverse transfer with a one-bit summing chip and, the second input of the third element I is connected to the second installation input of the second trigger, the output of the first element OR is connected to the installation input of the first trigger and the transfer output with a one-bit summing cell, the output of the first element I is connected to the information input of the second trigger, the first input of the first element I is connected with the first input of the second element OR, in each summing cell, the second input of the first element AND is connected to the second input of the second element OR and the second information input of the adder, the output of the inverse transferring each odnorazr summing discharge cell, except the first, is connected to an input of the inverse transfer the previous cell.