SU1570034A1 - Device for decoding voice signals - Google Patents

Abstract

This invention relates to radio. The purpose of the invention is to increase noise immunity with a simultaneous increase in the number of decoded frequencies. The device contains filter 1, comparator 2, frequency divider 3, counters 4, 5 and 6, block 7 for calculating the code of the input signal duration, switches 8 and 9, block 10 of permanent memory, block 11 of working memory, el-12 delays , register 13, descrambler 14, adder 15, block 16 comparing binary codes, distributor 17, electro AND 18 and 19, and electro OR 20 and 21. In this device, the process of decoding the signal is reduced to a calculation on the input of the input signal of the codes the duration of its periods and the comparison of these codes with the permissible values stored in the block 10 permanent memory. The data of this block by allowing them to change allows the optimal x-ki of the device to be selected. Since, in this device, recognition of the received frequency is performed immediately, this shortens the processing time and extends the range of processed frequencies. The device according to claim 2 is characterized by the execution of the calculation block 7. 1 hp f-ly, 3 ill.

Description

ate h

with

four

rator 2, divider 3 frequencies, counters 4, 5 and 6, block 7 for calculating the code of the input signal duration, switches 8 and 9, block 10 of permanent memory block 11 of the main memory, el 12 delay, register 13, decoder 14 , adder 15, block 16 for comparing binary codes, distributor 17, electro of AND 18 and 19, and electro of OR 20 and 21. In this device, the process of decoding a signal is reduced to a calculation of the duration of its periods and srav

The invention relates to radio and can be used to receive Tones of a number of predetermined frequencies, in particular for receiving data transmitted via a serial frequency code.

The purpose of the invention is to increase the noise immunity with a simultaneous increase in the number of decoded frequencies.

UA and FIG. 1 shows the structured: device of decoding tonal frequencies; on yshg. 2 is a block diagram of an input signal length code calculation block; on league. 3 - algorithm for the operation of the decoder tones: signals.

The device for decoding tones contains an input Ailter 1, a comparator 2, a divider 3 frequencies, the first 4, the second 5 and a third 6 counters, a block 7 for calculating the code time

the input signal, the first 8 and second 9 switches, block 10 of the permanent memory (BSH), block II RAM BOP, delay element 12, output register 13, decoder 14, adder 15, block 16 comparison of binary codes, distributor 17, the first 8 and second 19 elements And, the first 20 and second 21 elements OR. The input signal length calculation code unit 7 contains the first 22 and second 23 flip-flops, shift register 24, the first 25 and second 26 counters, the switch 27, the operational memory unit 28 (BOP), the first 29 and second 30 subtraction blocks, the input register 31,

The device works as follows.

Counter 6E changes its state with the frequency of the output signal

These codes with valid values are stored in the persistent storage unit 10. The data of this block by allowing them to change allows the optimal x-ki of the device to be selected. Since, in this device, recognition of the received frequency is performed immediately, this shortens the processing time and extends the range of processed frequencies. The device according to claim 2 of the Formula is characterized by the execution of the calculation block 7. 1 z.p., 3 ill.

0

five

0

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l 3 frequencies, determines the current time. The input sinusoidal signal that passes through the input filter 1, which improves the signal-to-noise ratio, is converted by the comparator 2 into rectangular pulses, which has the frequency of the input signal. On each edge of the signal at the output of the comparator 2, in block 7, the code of duration K (K-1), (K-2) ... (K-0) of the input signal is calculated by calculating the difference between the codes of counter 6 at the time of recording the arrival of the current the period of the input signal and the codes that had the counter 6 earlier, on K, (K-1), (K-2) ... (K-0) periods. The duration codes calculated in this way are successively fed to the information inputs of block 11, to the address inputs of which, via the first switch 8, from the output of the calculating block 7, codes defining the number of periods for which the duration is determined. The logical 1 signal from the control output of block 7 of the memory block 1i is switched to the recording mode (for recording information in the BOP And it is necessary that its logical input O signal be at its first input). After writing the duration codes K, (K-1) .., (K-0) of the periods of the input signal BOL 11 by the signal of logical 0 from the control output of the calculating unit 7, the address of the memory BOP 11 is determined by counter V55, since the first switch 8 is set to a state when the signal at its control input changes; at which KJ its outputs are received from the outputs of counter 5.

Counter 5 is a preset reversible counter operating in | subtraction mode. The logical 1 signal at its first input (installation input) at the outputs of counter 5 sets the code for the number that determines the maximum number of periods to be analyzed. With a logical O signal at the first input of counter 5, on each edge of the signal at its second (clock) input, the output code of this counter is decremented.

In the initial state, the code 5 is set at the outputs of the counter 5 and, therefore, initially the code 11 reads the code K for periods of the input signal, which through the second switch 9 is fed to the first address inputs of the block 10.

- Block 10 has two memory areas, the first of which is accessed with a logical O signal at its second (address) input, and the second with a logical 1 signal at the second input. In the first area, codes for the first address inputs of the second BSS area 10 are written, from which for each of the decoded frequencies it is necessary to start reading data when checking the compliance of the total duration K of a signal of a particular frequency with acceptable values (certain areas of address codes at the first inputs of the BOOP 10 corresponds to the entry on its first page of some numbers that uniquely correspond to the frequencies decoded by the device). In the second area, PPO 10 stores data defining the maximum allowable durations for each of the monitored amounts in K, (K-1), (K-2) ... (K-0) periods. The starting address for each of the decoded frequencies at which the code of the number, defining the maximum permissible duration of K periods, is stored in the second region of the BSP 10, is placed in the first BGN region 10. Increasing the code of this address by one when reading data from the second region gives the Bpp 10 the code of the number of the minimum permissible duration of K periods. At the following address, the code of the maximum permissible duration (K-1) of periods is stored, then the code of the minimum permissible duration (K-1) of periods, etc.

The delay element 12 inverts the control signal of the block.

0

five

7 and its delay: when a logical O signal arrives at the H input of delay element 12 at its output, during the time C, the logical O signal remains (the time must be equal to the total time required for reading data from the BOP 11 the delay time of the signal in the second switch 9 and the delay time for reading data from the control room 10. Therefore, after transferring block 11 to read mode, the initial readout of data is performed from the first

5 pages of block 10. In this case, a certain area of codes on the first inputs of PPU 10 corresponds to reading from its first page a number that uniquely identifies the starting address of the test, and hence the frequency to be decoded. Moreover, for preliminary deciding on the decoded frequency, you can use only the upper bits of the period duration K code read out of the BEP 11 (this is equivalent to dividing the number represented on the outputs of block 11 by 2, unless the least significant bit of the BOP 1 1 output code is used , and at 4,

0 if 2 bit bits are not used, etc.). Preliminary decision on the received frequency without taking into account the lower bits of the duration code K periods ensures a reduction in the volume of the BEP Y. The resulting error within the permissible deviations of the total duration K of the input signal periods is eliminated during subsequent tests.

When appearing at the output of the delay element 12 of the logical 1 signal, the output code of the block 10 is written into the parallel register 13. The switch 9 is set to the state

5 of which the output of the adder 15 is connected to the first inputs of the PPO 10. The output of the logic 1 delay element 12 also enables the operation of the distributor 17: at the signal of the logical

0 1 at its first (control) input and the logical O signal at its second input (P input). The signal fronts on its third (clock) input change the output signals of the 5 l. The adder 15 performs the summation of the codes of the register 13 and the first counter 4, initially set to zero. so reading data from the second area

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TU ™ 10 starts at the address specified by register code 13. At this address, a code is stored in LTP 10 that determines the maximum allowable duration K of the signal periods of the decoded frequency. Check if the total duration of several periods of the input signal is valid

The limiter 17 changes the states of the Form at its output a code of numbers (K-1), which ensures the readout of the block 1 1 of the number code determining the duration (K-1) of the period of the input signal. This code is similar to the one described in block 16 compared to the maximum and minimum

value is produced by comparing JQ with the values stored in

unit 16 comparing the numerical codes arriving at its first inputs (from the output of block 11) and to the second inputs (from the output of block 10). At the first output of the binary comparison block J 6, a logical 1 signal is generated,

the second region of the PPO 1 0. After this, the counter code 5 is decremented again, and the duration of the (K-2) periods, etc., is checked. If all the checks are performed (h corresponds to the installation at the output of counter 5 of the code of the number K- (0 + 1), then the output of the decoder 14, which is the clock output of the decoder,

the second area of the PPO 1 0. After this, the counter code 5 is decremented again and the duration (K-2) of periods, etc., is checked. If the conditions of all checks are performed (which corresponds to the installation at the output of counter 5 of the code of the number K- (0 + 1), then the output of the decoder 14, which is the clock output of the decoder, generates if the number represented by the code on its second inputs is greater than represented by a code at its second inputs. At the second output of block 16 Orav-2d, a signal indicating the reception of binary codes is a logical frequency signal whose code is set to

Which 1 is formed if

informational outputs of the decoder (outputs of the register 13). The occurrence of the sign represented by the code on the first inputs of block 16 is less than the number represented by the code on its second input 25 causes Logil Logical 1 to form at the clock output

Dah.

If the total duration of the K signal periods, defined by the code on the first inputs of comparison unit 16, is less than the maximum permissible value represented by the code on the second inputs of comparison unit 16, then its first output will be a logical signal that when the logo signal appears

ABOUT,

1 at the first entrance of the element

This AND 18 does not cause a change in the signal level at the output of this element. The positive edge of the signal from the first output of the distributor 17 through the element OR 20 of the counter 4 is transferred to the state 001 by the signal at its first (counting) input. In this case, the code at the output

the occurrence of a logical signal at the first output of the distributor 17, which will cause a logical 1 signal on

adder 15 is incremented by one. Since the outputs of the adder 15 through the output of the first element And 18, and then the switch 9 is connected to the first input, and at the output of the element OR the BPP 10, then the second inputs of the block 21. If, on the other hand, the total duration of 16 comparisons, the code that determines the minimum allowable duration K of the signal period of the decoded part of the monitored period is smaller than the set value, then the signal is logical 1, leading to initiality. If the total duration of the K-0 setting of the decoder, signal periods are generated that are read from the BOP at the output of the second element And 19.

11 is greater than the minimum permissible value, then the second output of the comparator 16 will be a logical O signal, and when the logical 1 signal arrives at the second output of the distributor 17, the state at the output of the element 9 does not change. Counter 5 on the signal front at the second output of races 700348

The limiter 17 changes the state to form at its output a code of a number (K-1), which provides for reading from block 1 1 the code of a number defining the duration (K-1) of the period of the input signal. This code, as described above, is compared in block 16 comparison with the maximum and minimum allowable values stored in

the second area of the PPO 1 0. After this, the counter code 5 is decremented again and the duration (K-2) of periods, etc., is checked. If the conditions of all checks are performed (which corresponds to the setting on the output of counter 5 of the code number K- (0 + 1), then the output of the decoder 14, which is the clock output of the decoder, generates a signal indicating that the frequency has been received

informational outputs of the decoder (outputs of the register 13). Signaling-Signaling Logil Logical 1 Signal Generation at Clock Output

At the output of the second element OR 21, the decoder returns to the initial state: the first counter 4 and the distributor 17 are reset by their second inputs (P-inputs), and the reversible counter 5 is reset. The initial setup signal is generated at the output of the second element OR 23 even if one of the test conditions is not met: if the total duration of the monitored sum of periods is more than the maximum set value, then the first output of the comparison unit 16 will be a logical signal 1

in my II 1 and

the occurrence of a logical signal at the first output of the distributor 17, which will cause a logical 1 signal on

output of the first element And 18, and, therefore, and at the output of the element OR 21. If the total duration

The code formation of the duration of the input signal is carried out in block 7 of the calculation as follows. On the front of the output signal of the comparator, which enters the input of the $ 25 counter, increases the code of its state, thereby determining the sequence number of the input signal period. Wherein

the trigger 23 at the clock input is set to the zero state. The output of the trigger 23 is connected to the first input / P input) of the shift register 24, Therefore, a signal 1 is set at the front of the signal input to the clock input of the shift register 24, at its first output (output of the first bit), which ensures writing to the register 31 code 0 set on the information inputs and characterizing the state of the counter 6 at the moment of arrival of the front of the input signal. By the logical 1 signal from the first output of the register. 24 the shift BOT7 28 is switched to the write mode, the switch 27 is set to the state where the outputs of the first counter 25 are connected to the first (address) inputs of the operative block 28. at the address determined by the sequence number of the input signal period, the output code of register 31, which characterizes the current arrival time of the input signal. On the next edge of the clock input signal, logical 1 appears at the second output of shift register 24, which flip-flop 22 is reset, forming a logical 1 signal at the control output and enabling the second (reversible) counter 26 to work. With the same signal, trigger 23 the second input (S-input) is set to one, the outputs of the shift register 24 are set to logic O, the BOP 28 is switched to read mode, and the outputs of the first calculator 29 are connected to its address inputs via switch 27 Ani. At the outputs of subtraction unit 29, the difference between the codes of two numbers is normalized: the output code of the counters 25 and 26. The output of the first counter 25 is set to the code of the sequence number of the input signal period. In the initial state, at the outputs of the second counter 26, the code of the number K is set - the maximum number of analyzed periods -. Therefore, the address number of the input signal, which was earlier in K periods, is formed at the address inputs of the BFR 28. This provides the reading from the BOP 28 cat and M counter 6, which he had previously on K periods of the input signal. At the output of the second subtraction unit 30, a code difference is generated (0 - M).

counter codes 6 at time points,. separated K.periodami analyzed signal. Since the counter 6 operates with the frequency fT

the occurrence of the leading edge of the input signal is noted by the state of counter 6, then the value (0 - M) f will determine the duration K of the periods of the input signal with an accuracy of up to a clock frequency period. The code for the duration of the input signal through the inLormation outputs is issued for recording to an external device simultaneously with the code for the number of periods for which it is defined (for this purpose, the address outputs are used). The counter 26 operates in the subtraction mode, therefore, with each pulse at its second (clock) input, its output code will be sequentially decremented by presenting the codes K, (K-1), (K-2), etc. at the outputs. Accordingly, on the other outputs there will be codes of duration K, (K-1), (K-2) periods of the input signal. During the formation at the second output of the counter 26 (transfer output) of the logical 1 signal, the trigger 22 at the second input is reset, which blocks the operation of the counter 26 and sets the number K code on its outputs. At the control output, a logical signal O is generated, which indicates the end of the calculation cycle of the analyzed signal durations,

Thus, the decoding process of the signal (Fig. 3) is reduced to calculating the K, (K-1), (K-2) ... (K-0) period duration codes on the input of the input signal and comparing these codes with valid values stored in block 10. At the same time, by increasing the output frequency of the splitter signal 3 frequencies and the constant value of the band at pickup. The permissible deviation values of the front input signal can reach several periods of the splitter signal. Moreover, the larger the difference of the numbers that determine the maximum and minimum total durations of several periods, the closer the shape of the frequency response of the device is to the rectangular one. Therefore, the deviation of the signal frequency within certain limits does not lead to a change in the reception probability. The control of each sum1

The duration of several periods is produced by comparing with the two extreme permissible values, regardless of how large the difference between them is. This makes it possible to increase the frequency of the divider 3 and thereby improve (the frequency of the decoder's frequency response without increasing the time spent on processing. At the same time, the response band is determined by the data of unit 10, which allows you to select the optimum characteristics of the device by changing them.

In the proposed device, the recognition of the received frequency is performed immediately, which shortens the processing time and extends the range of processed frequencies.

Claims (2)

1. A tone decoding device containing sequentially connected input filter and comparator, serially connected first counter and adder, sequentially connected second counter and decoder, the divider input is often 30 with the first output of the comparison unit connected to the corresponding input the main memory unit is the clock input of the device, as well as the first and second elements AND, the first element OR, the block of permanent memory, 35 output register and delay element, characterized in that increasing the noise immunity while increasing the number of decodable frequencies introduced unit 40 calculate a code length penalty Nala The signal input, first and second switches, the comparator binary codes, a distributor and a second OR gate, the output of the frequency divider 5 the third counter is connected to the information inputs of the code for calculating the duration of the input signal, to the signal input of which the comparator output is connected, information outputs ™ - the code of the duration of the input signal pair codes, the second output of which is connected to the second input of the first element, whose output is connected to the first the input of the second element OR, the second and third inputs of which are connected respectively to the output of the second element AND and to the output of the decoder, the first input of the first counter is connected to the output of the first element coagulant OR output of the second OR gate is connected to the second inputs of the first and second counters and the distributor, a clock input coupled to a clock input of the input signal duration calculating code block and an input of the frequency divider. 2. The device according to claim 1, characterized in that the calculating unit of the calculating unit for calculating the input signal duration code is connected to the corresponding inputs of the operating memory unit, to the address inputs of which the podna contains the first counter, the first subtraction unit, the switch, the operational memory unit and the second subtraction block, key corresponding outputs of j-r unit Other inputs of which connect the calculation of the input signal duration through the first switch to the other inputs of which the corresponding outputs of the second are counted with information inputs of the RAM block and outputs of the external register, successively connected first trigger and second count 12 and the control input of the first switch, the input of the delay element, and the control input of the RAM block are connected to the control output of the input signal length code calculation block, the outputs of the RAM block are connected to the corresponding inputs of the second switch and the binary code comparison block, the other inputs of which are connected to the outputs of the block of permanent memory and the information inputs of the output register, the outputs of which through the adder are connected to other inputs of the second switch, the outputs of which are connected with the inputs of the constant memory unit, the clock input of which is connected to the clock input of the output register, the control input of the second switch, the first input of the distributor and connected to the output of the delay element, the first output of the distributor is connected to the first inputs of the first AND element and the first OR element, the second input of which is connected to the second output of the distributor, the first input of the second counter and the first input of the second element I, the second input of which is connected to the first output of the comparison unit The code for the duration of the input signal pair codes, the second output of which is connected to the second input of the first element AND, the output of which is connected to the first input of the second element OR, the second and third inputs of which are connected respectively to the output of the second element And and the output of the decoder, the first input of the first counter is connected with the output of the first element OR, the output of the second element OR is connected to the second inputs of the first and second counters and the distributor, the clock input of which is connected to the clock input of the code calculation block lnosti input signal and the input of the frequency divider. laziness code of the duration of the SIG2. A device according to claim 1, characterized in that the computing unit comprises a first counter connected in series, a first subtraction unit, a switch, a random access memory unit and a second subtraction unit, unchanged with the information inputs of the RAM and the outputs of the input register, the first trigger and the second counter connected in series, the outputs of which are connected to the other outputs of the first subtraction unit, and the second trigger and the shift register connected in series, the upper output of which is connected to the control input of the input register, the switch and the RAM, the clock input of which is connected to the corresponding inputs of the shift-to register ha and the second counter is the clock input of the code length calculation module of the input signal, the first inputs of the first subtraction unit are connected to other inputs of the switch} 15 the first input of the first counter is connected the first input of the second trigger, the second input of which is connected to the second, the output of the shift register and the first input of the first trigger, the second input of which is connected to the second output of the second counter, and the inputs of the input register, the first input of the first counter and the second input of the second counter a are respectively the information, signal and clock inputs of the block for calculating the code of the input signal duration, the information, address and control outputs are respectively the outputs of the second subtraction block, the second counter and a second output of the first flip-flop. Figg Compiled by V. Evdokimova Editor N. Lazarenko Tehred L. Serdyukova Corrector O. Shotle Order 1460 Circulation 526 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5 Production and Publishing Combine Patent, Uzhgorod, st. Gagarin, 101 Subscription