SU1566457A1 - Amplitude modulator - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to reduce nonlinear distortion. The amplitude modulator contains 1 clock pulse generator, 2 pulse distributor, 3 address counter, Permanent-memory block 4, digital-to-analog converters (D / A) 5, 14, adder 6, controlled attenuator 7, power coupler 8, envelope detector 9, amplifier 10 , trigger 11, correction counter 12, operative memory unit 13, comparator 15, inverter 16 and AND elements 17.18. The goal is achieved by increasing the accuracy of the modulating signal correction, which is determined by the value of the lower bit of the DAC 14. 1 sludge.

Description

The invention relates to radio engineering and communications, measuring equipment and can be used to form amplitude-modulated signals in information transmission systems for various purposes.

The purpose of the invention is the reduction of nonlinear distortion.

The drawing shows a structural electrical circuit of an amplitude modulator.

The amplitude modulator contains a clock generator 1, a 2 pulse distributor, a 3 address counter, a constant memory unit 4, a first digital-to-analog converter (DAC) 5, an adder 6, a controlled attenuator 7, a power coupler 8, an envelope detector 9, an amplifier 10, a trigger 11, correction counter, block 13 operational memory, the second DAC 14, comparator 15, inverter 16, the first 17 and second 18 elements And

The amplitude modulator operates as follows.

The start signal at the first input of the trigger 11 sets the initial state of the counter 3 addresses, counter 12 correction and begins the formation of time-shifted pulses by the distributor 2, the input of which is connected to the generator 1 clock pulses. The sequence of addresses from the output of the counter 3 addresses the poll block 4, which records the sequence of code states of the modulating signal. From the output of the first DAC 5, a stepwise modulating signal through an adder 6 is fed to the modulating input of the controlled attenuator 7 and then to the power coupler 8. The envelope of the amplitude ~ modulated signal from the output of the envelope detector 9 through the amplifier 10 is fed to the input of the comparator 15. and is compared with the signal from the output of the first DAC 5, The error signal from the output of the comparator 15 through the inverter 16 and the elements And 17, 18 is fed to the inputs of summation and subtraction counter 12 correction, made in the form of a reversible counter, i I

From the output of the correction counter 12, the correction code is written to the block. · The correction code is read from block 13 by the address signals from the output of the 3 address counter, and after conversion to the second DAC 14, the analog correction signal is fed to the second input of the adder 6, In this case, the correction accuracy the modulating signal is determined by the value of the least significant bit of the second DAC 14, which allows to reduce the nonlinear distortion of the amplitude modulator.

Claims (1)

Claim An amplitude modulator comprising a serially connected controlled attenuator, a power coupler, an envelope detector, an amplifier and a comparator, wherein the second output of the power coupler is an output of an amplitude modulator, and the high-frequency input of a controlled attenuator is a carrier frequency input, characterized in that, in order to reduce non-linear distortion , introduced in series connected clock generator, pulse distributor, address counter, read-only memory, the first digital the analog converter and the adder, the correction counter, the operational memory and the second digital-to-analog converter, the inverter and the first element And, the second element And, the trigger, the first input of the trigger is the trigger input of the amplitude modulator, the address counter overflow output is connected to the second the trigger input, the output of which is connected to the installation inputs of the pulse distributor, address counter and correction counter, subtraction and summing inputs, to and, respectively, are connected to the outputs of the first and second elements AND, the second output of the pulse distributor is connected to the synchronization input of the correction counter, the installation input of which is connected to the output of the memory block, the third output of the pulse distributor is connected to the control input of the memory block, the address input of which is connected to the output kernel counter, the fourth output of the pulse distributor is connected to the second input of the first element And and the first input of the second element And, the output th analog converter connected to the second input of the comparator, whose output is connected to the input inverter and a second input of the second AND gate, the output of the second digital to analog converter connected to the second input of the adder, the output koto cerned is connected to the modulating input controlled attenuator.