SU1566376A1 - Series-parallel multichannel integrating converter - Google Patents

Abstract

The invention relates to a measurement technique, in particular, to devices for determining parameters of fast-repeating processes of short duration, and can be used in recording and monitoring integral parameters of signals. The aim of the invention is to improve the accuracy of the conversion by increasing the number of informative parameters and expanding the dynamic range by the joint transformation of the studied and approximate signals. The device contains the first group 1 multiplication units, integrators 2, generator 3 linearly independent functions, synchronization unit 4, device input 5, switches 6, sampling-storage units 7, adder group 8, first 9, second 10 and third 11 adders, multiplication unit group, multiplication unit 13, external input bus 14 informative parameters. The informative parameters obtained in the first cycle of conversion from the outputs of the integrators 2 in adders 9 and 10 form the signals bias and modulating, respectively: X _cm (T) = - ΣA _I1 ε _I (T)

X _M (T) = 1 + ΣA _I1 ε _I (T). In the second cycle, the signal [X (T) - X _cm (T)] is converted ^. X _m (T), and additional informative parameters allow to obtain weighting values {ε _I (T)} systems approximating functions by minimizing the expression _{{X (T) -ΣA I1 ε} I (T) - [ΣA I1 ε I ( T)] [ΣA _I2 ε _I (T)]} ² DT. 1 il.

Description

The invention relates to a measurement technique, in particular, to devices for determining parameters of fast-repeating processes of short duration, and can be used in recording and monitoring integral parameters of signals.

The aim of the invention is to improve the accuracy of the conversion by increasing the number of informative parameters and expanding the dynamic range by the joint conversion of the signal under study and approximation.

The drawing shows a block diagram of the converter.

The converter contains the first group of blocks 1-1 - 1-p multiplication, integrators 2-2 - 2-p, generator 3 linearly independent functions, block 4 of synchronization, input 5 of the device, switches 6-1 - 6-p, blocks 7-1 - 7-p sample-storage, the summation group of the ROI 8-1 - 8-p, the first 9, the second 10 and t ™ & 11 adders, the second group of blocks 12-1 - 12-n multiplication, the multiplication unit 1 and the outer input bus 14 informative parameters.

The mathematical justification for the operation of the device is as follows.

The conversion with respect to the direct parallel type converter involves the product of the sum of the signals: the studied x (t) and the offset xc (t), obtained from the inverting output of the first adder 9, and the modulating signal xM (t), which is formed at the output of the second adder 10.

If in the first conversion cycle only the signal x (t) under study is involved, with Ј0 (t) 1, xsm (t) -O, xMVt) 1, then the approximating signal

p-1

 a-t Ј .. (t) by the criterion of minimum

(t) - Ј., Er (t) dt (1)

about

and from the requirement of converting the zero-partial derivatives of expression (1) to the parameters a ;, is determined from the system of equations

r I llCx (t) - -E a;, f. (t) (t),

i.o J, n-1

(2)

or

five

0

V

Ifj {| x (t) Ј.U.) Dt

n-i

 Za J Ј, (t) Ј. (T) dt),, n-1. J „J

"O Then

a j

n-i

 Z b. I;

J

 4 l

(3)

which allows you to specify the weights of the adders 8-1 to 8-n (b (J).

If at the beginning of the second conversion cycle, during the action of the sampling signal, the outputs of the integrators 2 and the values of the informative parameters obtained in the first cycle of the transducer are connected to the sampling-storage units 7

development, are rewritten into sampling-storage units 7, then

g-

) -Јai (., (Thxw (t)

P-1

 1 +. a) H

(four)

Then the total converted signal °

„, JQ obtained in the second cycle of the transform: .K (t) x (t) - Г aif, (t)

I 0

+ i1 ai e, (t)

(five)

zopani.

Extraction of additional informative parameters a} in the course of approximation is equivalent to the extension of the system of functions fF; (t) j to the system. Thus, the range of the input signal is extended by converting pi

and accordingly, the informative integral parameters in the second conversion cycle are

I2 (t) - E a ;, Ј (t) 1 +

O1-0

+ a Ј; (t) Ј. (t) dt j x (t) 1-0

n-i

L

t-o n- (

The selection of additional informative parameters a} in the approximation is equivalent to the extension of the system of functions fF; (t) j to the system. In this way, the input signal range is expanded by converting pi.

the difference x (t) - a (t) and increased

20 the number of informative parameters, the Converter works in the following manner

Each conversion cycle includes the following signal sequence 0 сигна p (t) y (t) clt + (t) - 25 catches on the corresponding block outputs

(6)

- .a..edС ,, Ј., (0

synchronization: the removal of the integrator reset signal, the generation of synchronization signals of the generator of linearly independent functions and the integration resolution. F (t) dt30 This performs the conversion,

  which ends upon expiration

time-off signal resolution

Moreover, the first term is zero, the integration. At the outputs of the integrat turn from (2) .r, the values of informative values are stored. 1566376

 7

6

h-1

(four)

I-, J x (t) - X a; Ј. (T) - 5, f, (t) Ј; (L) dt (9)

Ico

 H + Xc "(t) xM (t) .E., (T) dt,

five)

zopani.

The selection of additional informative parameters a} in the approximation is equivalent to the extension of the system of functions fF; (t) j to the system. In this way, the input signal range is expanded by converting pi.

the difference x (t) - a (t) and increased

20 the number of informative parameters, the Converter works in the following manner

Each conversion cycle includes the following signal sequence (6)

Note that the minimum expression

35

J {x (t) - t a (, Ј. (T) - tSa; iE, (t) Z a, lЈ (t) J dt

1.0 1 0 - 1 J

(7)

45

sampling resolution, which ensures the memorization of informative parameters in the sampling and storage devices. At the end of the signal, the 4Q resolution is not set again.

the reset signal of the integrators, preparing them for the next conversion cycle.

If the simplest mode corresponding to the algorithmic description is used, then the inputs of the informative parameters when applying the zero values of the signals are the inputs of the initial setup, the conversion is performed only for the signal x (t). If the shape of the signal under investigation is predicted in advance, the prior information allows subtracting the xCM (t) signal from the x (t) signal and modulating the difference with the XM (t) signal, which predetermines the flow of the corresponding informative data.

The left part of this system is equal to the parameters of the bus 14.

It forms the integral vector 1. The following mode is also possible, when the initial setup does not fulfill the conditions for the vanishing of the partial output in terms of the parameters a; tj is achieved when

L

(t) - Z a ;, Ј, (t) Jx

about

P-1

(E; (O Ј; (t) dt

1 "About

(eight)

50

n-t

Z f-.o

((t) Ei (t) dtj.i 0, n-1.

parameters. A signal is then issued.

sampling resolution, which ensures the memorization of informative parameters in the sampling and storage devices. At the end of the sampling signal, it is set again.

(7)

45

(eight)

50

156363

Ij in the kth cycle are associated only with the parameters I, obtained in the previous cycle about

Claims (1)

The invention is a serial-parallel multi-channel integrating converter containing a synchronization unit, the start input of which is connected to the information input of the device, and the first output is connected to the generator input of linearly independent functions, the outputs of which are connected to the first inputs of the corresponding n multiplication units of the first group (where n 1, 2, ...) the second inputs of which are interconnected, and the outputs n of the multiplication units of the first group are connected to the information inputs of the corresponding n integrators, the output which are outputs of the device, characterized in that, in order to increase the conversion accuracy by increasing the number of informative parameters and expanding the dynamic range by jointly converting the studied and approximating signals, n switches, n sample-and-hold blocks, a group of n adders, the second group of n multiplicators, the first, second and third adders and the multiplier block, with the outputs n and 10 15 20 25 thirty tributes to the informative parameters of the device, and the outputs n of the switches are connected to the information inputs of the corresponding n sample-storage blocks, the output of the 1st (where, 2, ..., i, of the sample-storage block is connected to the i-th input of each of the n adders groups whose outputs are connected to the first inputs of the corresponding n multiplication units of the second group, the second inputs of which are connected to the corresponding outputs of the generator of linearly independent functions, and the outputs n blocks of the multiplication of the second group are connected to the corresponding n inputs of the first adder and with the corresponding n inputs of the second adder (n + 1) -th input of which is connected to the first output of the generator of linearly independent functions, the inverting output of the first adder is connected to the first input of the third adder, the second input of which is connected to the information input of the device, the output of the third adder is connected with the first input of the multiplication unit, the second input of which is connected to the output of the second adder, and the output of the multiplication unit is connected to the second inputs n of multiplication units of the first group, second, third, fourth and fifth outputs the synchronization unit is connected respectively to the integrator integration inputs n, to Tegrators are connected to the first information-35 | reset inputs of n integrators, to the main inputs of the corresponding n control inputs of the n switches and switches, the second information to the inputs of the sample n blocks of the sample whose inputs are connected to the storage input. five 0 five 0 eight informative parameters of the device, and the outputs of the n switches are connected to the information inputs of the corresponding n blocks of sample storage, the output of the 1st (where, 2, ..., i, of the sample storage) is connected to the i-th input of each of the n adders of the group The outputs of which are connected to the first inputs of the corresponding n multiplication units of the second group, the second inputs of which are connected to the corresponding outputs of the generator of linearly independent functions, and the outputs of the multiplication units of the second group are connected to the corresponding n inputs of the first adder and with the corresponding n inputs of the second adder, (n + 1) -th input of which is connected to the first output of the generator of linearly independent functions, the inverting output of the first adder is connected to the first input of the third adder, the second input of which is connected to the information input of the device, the output of the third adder is connected with the first input of the multiplication unit, the second input of which is connected to the output of the second adder, and the output of the multiplication unit is connected to the second inputs n multiplicators of the first group, second, third, fourth and fifth outputs the synchronization unit is connected respectively to the integrator integration inputs n, to