SU1562893A2 - Time-coded converter - Google Patents

Abstract

The invention relates to a measurement technique and can be used in radar and nuclear physics in measuring and converting time intervals. The aim of the invention is to improve the stability of the time scale of the time-code converter. The time-to-code converter contains a reference generator 17, forming triggers 13 and 20, counting ambiguity blocks 15 and 18, elements AND 14, 16, 22, delay element 21, element OR 24, time scale converter 25, key 19, counters 23 and 26 pulses. An additional generator of 1 pulses, RS trigger 3, elements 2, 4, 5, 8, 9, 10, 27, 28, elements OR 7 and 12, one-shot 6, counters 30 and 31 pulses, arithmetic logic unit are introduced into the converter 29, a digital-to-analog converter 11. The purpose of the invention is achieved by introducing new elements and forming new connections between all elements of the device. 2 Il.

Description

20

performs the selection of the time interval of the converter K, i.e. when pony t is between the leading edges of the start pulse and the first pulse following it, the reference generator 17. With the arrival of the stop pulse, trigger 20 is triggered, providing at the output of block 18 accurate synchronization with the pulses of the reference generator 17 of the end of the measured time interval. When this output pulse unit 18 stops the flow of pulses of the reference generator 17 through the element 16 on the counting, the input of the counter 23 pulses. The output pulse forming the trigger 20, delayed by the delay element 21, is fed to the input element And 22, the output of which is the selection of the time interval t between the leading edges of the pulses of the reference generator 17 and the Stop signal. The output pulses t {and t elements And 14 and 22 through the element OR 24 are fed to the input of the time scale converter 25, and then increased by K times in duration from the output of the time scale converter - to the input of the key 19, allowing the pulses of the reference generator 17 to pass through the key 19 to the first input of the counter 26 pulses. When, where T is the period of the reference generator 17, the overflow pulse arising in the counter 26 arrives at the third input of the counter 23 of pulses and the first input of the And element 27.

Control mode is provided to stabilize the K conversion factor. The principle of operation of the proposed converter is based on

By giving a time interval equal to T to the input, all the triggers of this counter are triggered, and an overflow pulse arises.

Therefore, when time intervals equal to TC or T are received at the input of the address counter, the counter records the same value only under one condition: when the coefficient

25 is exactly equal to K. This circumstance is used in the operation of the device for stabilizing the conversion coefficient. The stability of the conversion coefficient is determined only by the stability of the period of the reference oscillator. Since the frequency of the reference generator is not synchronized with the frequency of the pulse generator, the arrival at the input of the converter

l time intervals equal to Tk and

40

that in the Control mode, when the time converter arrives at the input, the code is of the same time intervals, the input of the converter, after adding the dominant time segments of the start and stop channels,

T., random and equipotent at. In the Monitoring mode, the proposed converter works as follows.

The external control receives a signal that switches the RS-flip-flop 3, the output signal of which blocks the arrival of Start and Stop pulses to the input of the time converter – code. The signal from the inverse output of the RS flip-flop 3 opens the element AND 2 and 4, allowing the Start and Stop pulses from the generator I output pulses to flow through the elements OR 12 and 7 to the input of the time-code converter. The output signal of the RS-flip-flop 3 triggers the one-shot 6, the output pulse of which sets the counters 30 and 31 of the pulses and the arithmetic logic unit 29 to the initial state. In addition, the signal from the inverse output of the RS flip-flop 3 opens the AND 5 element, enabling the pulses. from exit pos50

55

Vani transducer K, i.e. when a time interval equal to T is applied to the input, all the triggers of this counter are triggered, and an overflow pulse occurs.

Therefore, when time intervals equal to TC or T are received at the input of the address counter, the counter records the same value only under one condition: when the coefficient

conversion is exactly equal to K. This circumstance is used in the operation of the device for stabilizing the conversion coefficient. The stability of the conversion coefficient is determined only by the stability of the period of the reference oscillator. Since the frequency of the reference oscillator is not synchronized with the frequency of the pulse generator, the arrival of the converter K at the input, i.e. with on

l time intervals equal to Tk and

T., random and equipotent at. In the Monitoring mode, the proposed converter works as follows.

The external control receives a signal that switches the RS-flip-flop 3, the output signal of which blocks the arrival of Start and Stop pulses to the input of the time converter - a code. The signal from the inverse output of the RS flip-flop 3 opens the element AND 2 and 4, allowing the Start and Stop pulses from the generator I output pulses to flow through the elements OR 12 and 7 to the input of the time-code converter. The output signal of the RS-flip-flop 3 triggers the one-shot 6, the output pulse of which sets the counters 30 and 31 of the pulses and the arithmetic logic unit 29 to the initial state. In addition, the signal from the inverse output of the RS flip-flop 3 opens the AND 5 element, enabling the pulses. from the pic

the last trigger of counter 23 impulse ™ go to the pulse counter 30, if a short time interval T arrives at the input of the time scale converter 25, or a pulse time counter 31, if a long time interval arrives at the input of the time scale converter 25 ETC During the operation of the device in the control mode, the pulses of the code through the And 5 element arrive at the second input of the arithmetic logic unit 29s where the n-bit code is fed or subtracted to the information inputs of the arithmetic logic unit 29 from the counter 26 pulses. After the sweepers 30 and 31 are filled with pulses, an AND 10 element triggers, the output pulse of which, being fed to the control input of the digital-to-analog converter 11, allows the resulting n-time ™ serial code to be converted into an analog value that controls the conversion rate of the time converter 25 of the output pulse element 10 restores the RS-flip-flop 3 "including the converter vrmm - the code into the operating mode. With the arrival of an external control signal, the control cycle of the device is repeated,

The proposed converter is implemented on integrated circuits of the K 155 series, K 555, K 572, Blocks 15 and 18 of the sampling ambiguity can be performed on two D-flip-flops connected in series, As the elements And 2e 4P 5E 8, 300 14, i & j 22, 2.7, 23 and elements OR 7, 12, 24 used K 155 LAZ chips, one-shot 6 can be built on K 155 AGS, counters 23, 26, 30, 31 ichthulses - on K 155 ИЕ6, arithmetic logic unit 29 - on K 573 RF1, digital-to-analog converter I - on K 572 PA1, BS-trigger 3 - on K 155 T112, generator of aper torus pulses - and a K 355 A H,

The use of the proposed converter, which implements the method of stabilizing the conversion coefficient of the interpolation transducer, time code, allows to improve the stability of the cosfip, the conversion by

9

five

Q 5

five

0

Claims (1)

Invention Formula Time converter - code on author. St. By 1251707, characterized in that, in order to increase the stability of the converter's conversion coefficient, an additional pulse generator, a short-circuit trigger, eight I9 elements, two OR elements, a single vibrator, two pulse counters, an arithmetic logic unit, a digital-to-analog converter, the first output of the pulse generator is connected to the first input of the third element I, the second input of which is connected to the inverse output of the RS flip-flop, the first input of the fifth element I, the input of the single-oscillator and the second input of the fourth element AND, the output of which is connected to the first input of the second element OR j, the second input of the cochyme is connected to the output of the second element I5; the first input of which is connected to the external bus Stop, the first input of the first element AND is connected to the second input of the second element AND and the direct output RS - t-rigger ,, R-input of which is connected to the EAT by the control bus Control f S-input RS-trigger is connected to the output of the eighth element I and the control input of the digital-to-analog converter, the second input of the first element and connected to the external bus Start, the output of the first element connected to the first input of the first OR element, the second input of which is connected to the output of the third AND element, the output of the first OR element is connected to the first input of the first forming trigger of the time – code converter, the first input of the second forming trigger is connected to the output of the second OR element, the output of the last trigger the coarse meter counter is connected to the second input of the fifth element I, the output of which is connected to the first inputs of the sixth and seventh elements AND and the second input of the arithmetic logic unit, outputs the seventh elements And are connected to the inputs of the first and second pulse counters, respectively, the outputs of the first and second pulse counters are connected to the first and second inputs of the eighth element And and the second inputs of the sixth and seventh elements And, respectively, the output of the spinner is connected to the control inputs of the first and the second pulse counters and with the third input of the arithmetic logic unit, the outputs of which are connected to the information inputs of the digital-to-analog converter, the output of which is connected to the control input A time converter, direct and inverse outputs of the overflow trigger The inputs of the sixth and seventh elements And, respectively, the third input of the seventh element And is connected to the first input of the arithmetic logic unit, the information outputs of the counter of the exact measurement of the time converter - the code is connected to the information inputs of the arithmetic logs accurate measurement connected to a third-jq device, FIG. 2