SU1647510A1 - Time intervals meter - Google Patents

Abstract

This invention relates to a measurement technique. The aim of the invention is to improve the measurement accuracy. A device for measuring time intervals contains a generator of 1 exemplary frequency, two blocks of 2.3 matches, an element of OR-NOT 5, counters 6, 13, 14 pulses. D-triggers 7, 8, 11, two vernac generators 9, 10, block 18 digital readout. An inverter 4, D-flip-flop 12, RS-flip-flop 17, logical element OR-NOT 16, logical element EXCLUSIVE OR 15 are introduced into the device. By introducing new elements and forming new connections, the goal of the invention is achieved. 3 il.

Description

The invention relates to a measurement technique and can be used to measure short time intervals.

The aim of the invention is to improve the measurement accuracy by eliminating a gross counting error.

Fig. 1 is a functional diagram of an apparatus for measuring time intervals; figure 2 - timing charts of his work; on fig.Z - timing charts of the device when measuring pulses with a duration of less than 100 no.

The output of the pulse generator 1 is connected to the first inputs of the matched blocks 2.3 and the input of the inverter 4, the output of which is connected to the second input of the element OR- NOT 5, the output of which is connected to the counting input of the counter 6. The input buses are connected to the R inputs of the D-flip-flops 7 and 8 respectively, their outputs are connected to the inputs of the Vernier generators 9 and 10 pulses, respectively, and to the C inputs of the D-flip-flops 11 and 12, respectively. The output of the Vernier generator 9 is connected to the counting input

the counter 13 and to the second input of the block 2 match, the output of the last is connected to the C input of the trigger 7. The output of the Vernier generator 10 is connected to the counting input of the counter 14 and the second input of the block 3 match, the output of the last is connected to the C input of the trigger 8. Pr my trigger output 11 is connected to the first input of the EXCLUSIVE OR 15 element and to the first input of the OR-NOT element .16. The direct and inverse outputs of the trigger 12 are connected to the second inputs of the EXCLUSIVE OR 15 element and the OR-NOT 16 element. The output of the latter is connected to the S-input of the trigger 17, the output of which enters the sign N0 of the digital reference block 18, the other three groups of its inputs are connected to the output groups of counters 6. 13, 14, respectively. The third inputs of blocks 2 and 3 are matches, the inputs for setting zero counters 13. 14, the R inputs of the flip-flops 11, 12, 17 are connected to the reset bus.

The exemplary frequency generator 1 is designed to form a hundred pulse (L

WITH

about

4 vj

SL

frequency, made on the K500LP116 chip.

D-flip-flops 7, 8, 11, 12 and RS-flip-flop 17 are performed on a K500TM131 chip. The triggers 7, 8 are designed to control the vernac generators 9 and 10 and to control the triggers 11 and 12. The triggers 11 and 12 together with the logic element form an EXCLUSIVE OR 15 time interval T0, which is filled on the logical element OR-NOT 5 pulses of the inverted generator sequence 1 exemplary frequency.

The logical element EXCLUSIVE OR 15 is made on the K500LP107 microcircuit.

Logic elements OR NOT 16 and 5 are made on the K500LE211 microcircuit.

The logical element OR-NOT 18, together with the RS-trigger 17, is used to register the situation when the vernier generator 9 stops later than the vernial generator 10 stops.

The inverter serves to invert the pulse train of the generator 1 at an exemplary frequency.

Vernier generators 9 and 10 are designed to form a sequence of pulses triggered by the arrival of Start and Stop pulses, respectively, and stop when their phases coincide with the generator phase of exemplary frequency 1, performed on an " 500 L M105 chip.

The counters 13, 14 and 6 are designed to count the pulses of the sequences produced by the Vernier generators 9 and 10 and the generator 1 of the reference frequency, respectively. Made on chips K500IE136.

Blocks 2 and 3 of coincidence are designed to isolate the moments of coincidence of the phases of the Vernier Generators 9 and 10, respectively, with the phase of the generator 1 of exemplary frequency and are performed on the K500TM131 chip, the first, second and third inputs of the coincidence block correspond to D-, C- and R-inputs trigger respectively. The inverse trigger output corresponds to the output of the match block.

The digital readout unit 18 is designed to process the contents of the counters 13, 14, and 6, taking into account the state of the trigger 17.

The device for measuring time intervals operates as follows.

Before the start of the measurement, the triggers 11, 12 and 17, the counters 13, 14, and b blocks 2 and 3 of the match are reset by the Reset signal. Upon the arrival of the start-pulse, the trigger 7 starts the vernier generator 9, the counting pulses of which start to arrive at the counting input of the counter 13 and at the same time at the coincidence unit 2, where the moment of the coincidence of the phases of the pulses of the vernier generator 9 and the pulses of the continuously operating generator 1 of the reference frequency occurs. The signal produced by coincidence block 2 closes trigger 7, which, in its

the queue stops the generator 9 and starts the trigger 11.

Upon the arrival of a stop pulse, trigger 8 starts the vernier generator 10, pulses

which start to arrive at the counting input of the counter 14 and the block 3 of coincidence to generate the moment of coincidence of the phases of the pulses of the generator 1 exemplary frequency and generator 10. The signal generated by the block 3 of coincidence closes the trigger 8, which, in turn, stops the generator 10 and starts the trigger 12.

Trigger signals 11 and 12 on the logic element EXCLUSIVE OR 15

form a strobe, which on the logical element OR-NOT 5 is filled with pulses of the generator 1 of exemplary frequency. Next, the signal from the logical element OR NOT 5 arrives at the counting input of counter 6.

The pulses of the generator 1 of the exemplary frequency are fed to the gate of the OR-NOT 5 logic element through the inverter 4 to eliminate ambiguity zones when counting pulses in the counter 6.

The contents of the counters 13, 14 and 6 are converted in block 18 of the digital readout into a code corresponding to the value of the measured interval.

The operation of the device is explained by the timing diagrams shown in Figures 2 and 3. The measured interval Tx (Fig. 2a) is set by start and stop pulses (Fig. 2b and Fig. 2c, respectively) and is represented as

Tx Ti-T2 + To, - O)

where Ti is the operating time of the generator 9, quantitatively equal to the number of its oscillations NI during this time interval (Fig. 2d) multiplied by its period;

Ta is the time of generator 10 operation, it is quantitatively equal to the number of its oscillations N2 over this time interval (Fig. 2 d), not its period multiplied;

Then, the time between the moments of coincidence of the phase 1 generator of the reference frequency with the phases of the Vernier generators 9 and 10, is quantitatively equal to the number of oscillations No of the model oscillator 1 (FIG. 2e) for etrt the time interval (FIG. 2g) multiplied by the period of the generator 1.

The division of the measured time interval into such three intervals solved the problem of docking coarse and accurate measurement scales, since the boundaries of all three intervals are rigidly connected with the phases of the counting pulses filling them, therefore, there is no gross counting error when measuring the T0 interval. FIG. 3 shows a case that can occur when measuring short pulses (less than 100 ns). In this case, the measured interval Tx can be written as

Tx - Ti - T2 - T0. (2)

In order to register this situation, the device ORIEN 16 and the trigger 17 are provided in the device circuit, from which the signal used to select the formula for calculating the value of the measured interval is removed.

Based on the fact that the period of the generator 1 is equal to r, the periods of the vernial generators 9 and 10 are chosen equal to t minus one counting unit, the formula (1) takes the form

Tx r (Ni-N2 + N0) - (Ni-N2), (3)

and formula (2) takes the form

Tx r (Ni-N2-N0) - (Ni-N2). (4)

Due to the fact that the vernial generators 9 and 10 are identical and tuned to the same frequency, the additional measurement error is reduced, since the formulas (Nt – N2) from these generators are included in formulas (3) and (4).

The use of the proposed device makes it possible to increase the accuracy of the measurement of time intervals with ± 16 not in the known device to ± 2 ns.

Claims (1)

Invention Formula A device for measuring time intervals, containing a generator of exemplary frequency, the output of which is connected to the first input of the first and second blocks of coincidence, the first, second and third D-triggers, the OR-NOT logical element, the output of which is connected to the counting input the first counter, the second counter, the counting input of which is connected to the output of the first nonius generator, whose input is connected to the output of the first trigger, and to the second input of the first coincidence unit, the output of which is connected to the C input of the first trigger, whose R input is connected to the trigger bus , the third counter, the counting input of which is connected to the output of the second vernac generator, the input of which is connected to the output of the second trigger, and to the second input of the second coincidence unit, the output of which is connected to the C input of the second D-trigger, R input They are connected to the stop bus, and the groups of outputs of the first, second, and third counters are connected to the first, second, and third groups of inputs of the digital readout unit, respectively. that, in order to improve the measurement accuracy, a fourth D-trigger and an RS-trigger, an inverter, a second OR OR element and an EXCLUSIVE OR logic element are introduced in it, the output of which is connected to the first input of the first OR element OR, the second input of which connected to the inverter output, the input of which is connected to the generator output of the reference frequency, the output of the first D-flip-flop is connected to the first C-input of the third D-flip-flop, the output of which is connected to the first input of the second OR-NOT element and the first input of the EXCLUSIVE OR element, the second log in which is connected to the direct output of the fourth D-flip-flop, the first C-input of which is connected to the output of the second D-flip-flop, the inverse output of the fourth D-flip-flop is connected to the second input of the second OR-NOT element, the output of which is connected to the S-input of RS -trigger, the R-input of which is connected to the reset bus, to the R-input of the third and fourth D-flip-flops, to the installation inputs of the first, second and third counters, to the third input of the first and second coincidence blocks, the RS-flip-flop output is connected to the fourth input block digital readout. 51 13 one J Tire. stop ° rt vfcU to ow w L if7 I f ftf. W2 at Wo 5ta Wfl I $ “§ B1 b I Tire FIG 1 reset B L five J gsh I PPT well s four P 2 7 Ppp p pppt - then pppg Jdl Faye. five