SU1559432A1 - Device for analysis of addressed message - Google Patents

Abstract

The invention relates to communication technology and can be used in devices for receiving code combinations of the type of M-sequences. The purpose of the invention is to improve the accuracy of the analysis of multi-position address packages with a variable number of positions. The device contains a shift register 1, a sync pulse allocation unit 2, a frequency divider 3, an adder unit 4, a number setting unit 5, a switch 6, triggers 7 and 14, a parcel counter 8, counters 10 and 15 positions, a timer 11, an OR element 12 and a block 13 indications. The device has an increased accuracy of analysis by eliminating false positives, and also provides an analysis of group call address packages that have a variable message length. In this case, the higher the priority of the call, the shorter the length of the address package. 2 ill., 1 tab.

Description

The invention relates to communication technology and can be used in devices for receiving code combinations of the type of M-sequences. $

The purpose of the invention is to increase the accuracy of the analysis of multi-position address parcels with a variable number of positions.

Figure 1 shows the structural Yu diagram of a device for the analysis of address sprinkles; in FIG. 2 - frequency divider.

The device contains (Fig. 1) a shift register 1, a sync pulse allocation block 2, a frequency divider 3, an adder block 4, a number setting unit 5, a switch 6, a first trigger 7, a parcel counter 8, an input 9 of the device, a first counter 10 positions , 20 timer 11, OR element 12, display unit 13, second trigger 14 and second position counter 15.

The frequency divider (Fig. 2) contains a pulse generator 16, an equivalence element 25 17, a counter 18, a decoder 19, a dialing unit 20, a Multi-t plexor 21 and a counting trigger 22.

The operation of the device consists in decoding the address combination jq consisting of several successively following code combinations, each of which is an M-sequence, and checking it for correspondence to the subscriber number. The amount of $$ in the codes of M-sequences that are part of the address sprinkling, as a rule, is 10 (A). The number of consecutive combinations K corresponds to the number of positions in the address parcel.

The total number of possible ^ address ^ -th packages of C-AK, C also means the number of subscribers in the network. So, with А “10 and К ^е 5 С = 10 ^s = .100000 (subscribers 45 tov).

The principle of operation of the device is reduced to the analysis of the next position (M-sequence) and, with a positive analysis result, the device switches to the analysis of the next position. In the case of a positive analysis of all positions, a decision is made to accept the address sprinkling by the subscriber.

A group call signal is a combination of M-sequences (usually the eleventh) that corresponds to a circular call.

If the M-sequence corresponding to the circular call follows in the last K-th position, then a group of subscribers is called whose numbers coincide up to the last character (with A = 10, 10 subscribers are called).

If the M-sequence corresponding to the circular call follows in the first position, then all subscribers are called. In the general case, 1, 10,100 ... 10 ¹⁴ subscribers can be called (at A = 10), while 1 subscriber is called in the absence of an M-sequence of a circular call.

For example, if there are subscribers in the radio network with numbers from 00000 to 99999 and a 565 V signal is transmitted, then all subscribers with numbers from 56500 to 56599 are called.

The signal from the input of the device 9 is fed to the information input of the shift register 1, to the input of the block 4 adders, to the frequency divider 3 and to the input of the block 2 allocation of clock pulses. The shift register 1, consisting of N bits, stores the values of the previous N signals. Block 2 sets the frequency divider .3 to the zero position at the moments of the leading and trailing edges of the pulses, which ensures the issuance of pulses of advancement of information at times that coincide with the middle of the elementary premises. The adjustment of the phase following the pulses of information advancement is ensured at the moments of changing the polarity of the input signals, due to which an error connected with fluctuation of the edges of the input signals is connected. The outputs of the bits of the register 1 shift are connected to the block 4 adders.

Block 4 consists of a set of adders modulo two, the number of which corresponds to the number of analyzed code combinations of M-sequences (usually 11), each of the adders is connected to the input of device 9 and to the corresponding outputs of shift register 1 (the number of connected outputs of the shift register can be from 2 to N in accordance with the generating polynomial of a code of type M sequence). The analysis of code combinations for their belonging to one of 11 possible sequences is performed simultaneously and simultaneously.

The results of the summation from block 4. go to the second trigger 14 and to the inputs of block 5 setting the number. Block 5 has K outputs, which, when assigned to a device, are connected to the corresponding inputs of the same block. For example, to set the number 50569, it is necessary to respectively connect the 1, 2, 3, 4, 5 outputs with the 5.0, 5 ^ 6, 9 inputs of the unit for setting the number 5, Figure 1 conditionally shows the setting for the number 90, .. 9,

The switch 6 in accordance with the state of the counter 10 positions provides alternating, starting from the first, the connection of the outputs of the unit 5 setting the number to the information input. the first trigger 7, which provides element-by-bit recording and inter-cycle storage of the summation results, and, in the case of receiving M-sequences corresponding to the set number, the first trigger 7 captures the zero state in each clock cycle. The zero-state signal from the output of the first trigger 7 arrives at the enable input counter 8 parcels, puts the latter in counting mode. The counter 8 toppings counts consecutively correctly received elementary premises (ticks). If their number exceeds the threshold value B (where B is the value that determines the number of checks necessary for reliable reception of the M-sequence), the counter 8 sends a signal to translate the first counter 10 positions and the associated switch 6 to the next state. In the event that in the process of counting elementary premises at least one of them turns out to be affected, as well as when receiving someone else's sequence, individual signals arrive at the resolving input of the counter of 8 toppings, which translate it into a zero (initial) state. The counter 10 positions on the signals from the counter 8 parcels are sequentially transferred from the initial state corresponding to the reception of the first position, in subsequent states until it reaches the (K + 1) -th state, after which it returns to its original state. Finding a position counter in the (K + 1) -th state is a sign of receiving an address sprinkle. In order to avoid blocking the device (ensuring that it returns to its original state), the device contains a timer 11, which ensures that the counter 10 positions' 10 are reset to the initial state each time a signal to receive the next position from the counter 8 toppings is not received at all or arrives late.

- The response time of timer 11 is set equal to 1.5 T, where T is the time interval for following the first, second, etc. positions (one M-sequence). With the normal reception of your own address package, pulses from the counter 8 toppings come with a period equal to T, and each time reset timer 11 to its original (zero) state, thereby excluding the appearance of a signal at the timer output 25

11, and consequently, the reset of the first counter 10 positions in the initial state.

Thus, the device provides 3Q analysis of the multi-position address sending of the individual subscriber number and fixation in block 13, where the signal comes from the output of the counter 10 positions through the OR element 12.

A group call signal is received similarly to an individual one, and the M-sequence corresponding to the circular 4Q call is allocated using the second trigger 14 and the second counter 15 of the packages and, if received correctly, is fixed in the display unit 13 via the element 45 OR 12, which indicates display unit priority of the address package. With a circular call in the first position, a zero priority is fixed, indicating that all subscribers are called 5Q, when a circular call is received in the first position, the first priority is fixed, etc. In the absence of a circular call in the address powder, the lowest priority is fixed in the display unit, numerically equal to the number of positions in the address package.

In order to eliminate false alarms of the device, the signal positions differ from each other by the durations of single and zero symbols of Sequences. Reception of such positionally encoded M-sequences is carried out using a frequency divider 3.

The frequency divider 3 is a controllable pulse frequency divider. The division frequency is controlled by a code generated by the counter of 10 positions and the current information symbol from the input of the device 9,

The functional diagram of the frequency divider 9, 5 (figure 2) provides the following way,

In accordance with the control code supplied to the inputs ΑΙ,.,., Αά of the multiplexer 16, which switches 20 of one of the inputs XI, ..., X with its own output, for example, at 00 ... XI is switched, ' ₍

The indicated code corresponds to the reception of: the first position of the composite device sequence and the action of the zero character at the input of the device 9. When changing the character to a single (Al =? L) multiplexer 16 switches to its output X2. Thus, 30 when changing characters, XI and X2 of multiplexer 16 are alternately switched. When changing the state of the counter, 10 positions :: are 100.,. the inputs of X3, X4 of the multiplexer 16, etc. are alternately switched.

The pulse repetition rate of the frequency divider 3, corresponding to each value of the combinations at the outputs A1, · .. ♦, Ad of multiplexer 16, is determined (set) using the dialing unit 20.

Figure 2 shows an example of setting frequencies according to table ₀

The table shows that in the first position of the composite sequence, the repetition rate of clock pulses corresponding to single and zero characters is the same and equal to l / 4f ₀ , and in the second position, the repetition rate of clock pulses when receiving single characters is half the repetition rate when receiving 0 characters. Moreover, the law of changing the repetition frequencies of clock pulses is determined by the law of code formation and should be the same at the transmitting and receiving ends; otherwise, the device for analyzing address dusts perceives them as a hindrance (alien Sequence).

The counter 18 and the decoder 19 of the frequency divider 3 provide a distribution of pulses in time, and the element 17 closes the feedback circuit of the reset counter 18. Having counted to a certain state, the counter 18 is set to zero by the signal from the element 17, and the frequency of (short) reset pulses is additionally is divided into two by counting trigger 22, providing a duty cycle of Fu pulses equal to 2.

The phase matching of clock pulses is carried out at the moments of changing the polarity of the input symbols, when the signal from block 2 through element 17 resets the counter 18 and the counting trigger 22 to zero (initial state).

The frequency divider 3 allows you to get up to (- ~ C) ¹ = K ^g non-repeating pairs of frequencies of repetition of clock pulses, with b 7 / s,

The introduction of variable clock intervals (clock frequencies) allows us to eliminate the false reception of an address packet containing the following M-sequences of the same name in a row, since M-sequences formed by the same coefficients of a primitive polynomial have different combinations of zero and unit durations in different positions characters, which allows them to effectively distinguish from each other.

Thus, the device has increased accuracy of analysis due to the elimination of false positives and provides an analysis of group call address packets with a variable message length, and the higher the call priority, the shorter the address message length, so the minimum sending time equal to one position corresponds to zero priority when the M-sequence corresponding to the circular call follows in the first and only in the first position.

Claims (1)

Claim. A device for analyzing an address sprinkle containing a shift register connected in series, the first input of which is combined with the inputs of the clock separation block and the adder block, a number setting unit, a switch, a first trigger, a parcel counter, a timer and a first position counter whose outputs are connected to the control inputs of the switch , the second input of the shift register is combined with the second inputs of the first trigger and the parcel counter, the output of which is connected to the second input of the first position counter, and the output of the block I have sync pulses. connected to the input of the frequency divider, the output of which is connected to the second input of the parcel counter, characterized in that, in order to increase the accuracy of the analysis of multi-position address parcels with a variable number of positions, a second trigger is connected sequentially · 5, the first input of which connected to an additional output of the adder block, a second position counter, an OR element, the second input of which is connected jq to an additional output of the first position counter, an indication block, the second inputs of which are connected to the outputs of the first position counter and combined with the second inputs of the frequency divider, the third input of which is combined with the first input of the shift register, the second input of which is combined with the second inputs of the second counter and second position counter. No pp A1 - A2 ----- h • about ·· · Position number Ad ^F tm 1 0 0 0 0 1/4 f ₀ 1 2 1 0 0 0 1/4 f ₀ 1 3 0 1 0 0 1/4 f ₀ 2 4 1 1 about 0 1/8 f ₀ 2 • Q • a • • • • • • • • • about • • • • • • ♦ S-1 l / 2c f ₀ C / 2 FROM l / 2c f ₀ C / 2