SU570212A1 - Device for phase starter for diserete information receiver - Google Patents

Description

I

The phase-start device for the receiver of discrete information relates to digital technology, in particular, to a 1-system5 synchronization disk and a device, with phase-start. It can be used in synchronization systems in which the adjustment of clock frequencies is made by a periodic CMR recurrent signal.

One of the well-known ,,, is a device in which the phase-up is carried out by supplying duplicate combinations, repeating n times, or by feeding a recurrent sequence of a certain length l3

With such a construction of phase synchronization systems, the information from the kotor can not be obtained from the preceding clock adjustment signal.

It is known a phase-start device for receiving disc information containing a series-connected switch, shift register, prohibition element, OR element, counter and trigger, output connected to the second end, the counter

The inputs of the corresponding shift register bits through the first comparison block are connected to one of the switch inputs and the second comparison block, the other inputs of which are interconnected, and the output of the second comparison block is connected to the second input of the OR element. In addition, a sequence of clock pulses is applied to the corresponding inputs of the shift register bits and to the clock output of counter 2.

However, to find the undistorted section of the phase-start signal, it is necessary that the filling of the shift register of the receiving device, with which this section is detected, does not contain distorted characters, which leads to an increase in the length of the undistorted section of the recurrent sequence, which determines the phase-start signal in turn, increases the duration of the signal & la phase start while maintaining the same probability of detecting the undistorted section.

The aim of the invention is to reduce the reception time of a phase-start signal while maintaining the likelihood of its correct reception. The goal is achieved by the fact that the known phase triggering device npneTviHHKa of discrete information containing a serially connected switch, shift register, prohibition element, OR element, Counter and trigger, is connected to the second input of the counter, and the outputs of the corresponding shift register through the first 6jioKs are connected to 8. one of the inputs of the switch and the second comparison unit, the other inputs of which are interconnected, and the output of the second comparison unit is connected to the second input of the element OR. The sequence of clock pulses is applied to the corresponding inputs of the shift register bits and to the clock input of the counter, inputting serially connected time sensor. The variable marks, the threshold block, and the And bits of the shift register are connected to the corresponding inputs of the time stamp sensor, the output of which is connected to the second input of the And element, and the BTOpos.y ax of the threshold block is connected to the second output. a unit of comparisons, in which case the trigger output is connected to the TjietbeMy input of the threshold unit and to the auxiliary input of the switch. The drawing shows a structural electrical circuit of the proposed device. It contains serially connected switch 1, shift register 2, prohibition element 3, element OR 4, counter 5 and trigger 6, the output of which is connected to the second input of counter 5, and the outputs of the corresponding bits of the shift register 2 through the first comparison unit. 7 are connected to from the inputs of the switch 1 and the second block of the comparison - 8, the other inputs, which are combined with each other, and the output of the second comparison block 8 is connected to the second input of the element OR 4, the sequence of clock pulses is fed to the corresponding inputs of the register bits and the shift 2 and the clock input of the counter 5, and the time sensor 9, the threshold unit 10 and the element 11, which are connected in series, and the outputs of the shift register 1 are connected to the corresponding inputs of the time stamp sensor 9, the output of which is connected to the second input element 11, and to the second output of the threshold unit 1O, the output of the second comparison unit 8 is connected, and the output of the trigger 6 is connected to the third output of the threshold unit 1O and the auxiliary input of the switch 1. The device operates as follows. A clock pulse is applied to the shift register 2 and the counter 5, and to the trigger 6 a pulse is set to the initial state. At the same time, input signals are fed to the input of shift register 2 through switch 1, counter 5 starts counting, the a-threshold block Ю is set, and trigger 6 returns to its initial state and is held in it. Comparison unit 7, according to the information recorded in shift register 2, generates a sequence of pulses with which, in comparison unit 8, the received input signal is compared. If there is interference or the clock frequencies of the receiving and transmitting stations are discharged, a pulse is generated at the output of the comparison block 8, sending counter 5 to the beginning of the count, and when the compared signals coincide, these pulses are absent, and the counter 5 counts the number of further undistorted characters. that signal. In the absence of a received signal at the device input, a prohibition element 3 is triggered and, through the OR element 4, resets counter 5 to the beginning of the count. When an undistorted section of a given length appears in the received clock adjustment check signal, the counter 5 forms at its output a pulse arriving at the previous part of the receiving side, which begins to transmit a response signal. The same impulse triggers trigger 6 / which, using switch 1, closes feedback of shift register 2, passing through comparison block 7, turns off counter 5 and enables the n-horn block 10 to work. At the same time, shift shift register 2 and comparison block start 7 sequences of synchronous and in-phase recurrent sequence, forming a clock adjustment signal, because by the time of feedback closure, shift register 2 is filled with undistorted symbols of the received clock adjustment signal by, and themselves receive clock frequencies tailored to transmit clock. On these synchronous sequences, synchronous time stamps are formed at the reception and transmission. On the receiving side, this is a sensor of time stamps 9. Simultaneously with switching the trigger 6 signal to a clock frequency, the counting of pulses starts from the output of the comparison unit by 8 threshold block 1O, which is reset to the initial counting conditions by pulses from the time stamp sensor 9. Pulse at the output of the block

Not more than 7 are formed with each mismatch of the symbols of the reference sequence coming from the comparison block 8 and the received signal. After it received: 1 by the transmitting side of the clock frequency adjustment confirmation, it synchronously with the time stamp starts transmitting the phase start signal, the inverse check signal of the clock Hat-TOT adjustment and terminates its transmission with the next time stamp, and the phase start on the transmit side. At the receiving unit with a phase start signal, the number of pulses at the output of the comparison block 8 increases compared with their number from interference and increases abruptly and the output of the threshold unit 10 generates and remembers the voltage allowing the time mark passing through the AI element to end mismatch. In this way, simultaneously on the transmission and reception of synchronous time stamps preceded by a phase start signal, a phase start is made.

In the proposed device phase

Claims (2)

1. USSR author's certificate number 315300, cl. H 04 L 7 / OO, 1971. 2. Martynov EM. Synchronization in systems for the transmission of discrete messages. Ed. References, M., 1972, p. 20O.