SU1541589A1

SU1541589A1 - Information input device

Info

Publication number: SU1541589A1
Application number: SU884404688A
Authority: SU
Inventors: Виктор Геннадиевич Елисеев; Владимир Иванович Плиш; Ярослав Владимирович Коханый
Original assignee: Предприятие П/Я В-8751
Priority date: 1988-04-04
Filing date: 1988-04-04
Publication date: 1990-02-07

Abstract

Изобретение относитс к автоматике и вычислительной технике и может быть использовано дл ручного ввода информации в устройства обработки. Целью изобретени вл етс повышение быстродействи устройства, которое содержит клавиатуру 1, мультиплексоры 2, генератор 3 импульсов, элементы И 5 и 6, элемент ИЛИ 7, элемент НЕ 8, триггер 9, счетчик 4, группу элементов И 10, группу элементов НЕ 14, группу элементов ИЛИ 13. Изобретение позвол ет повысить быстродействие устройства при одновременном уменьшении разр дности счетчика 4 и мультиплексоров 2. 1 ил.The invention relates to automation and computing and can be used to manually enter information into processing devices. The aim of the invention is to improve the speed of the device, which contains a keyboard 1, multiplexers 2, a generator of 3 pulses, the elements 5 and 6, the element OR 7, the element 8, the trigger 9, the counter 4, the group of elements 10, the group of elements 14, group of elements OR 13. The invention allows to increase the speed of the device while reducing the bit size of the counter 4 and multiplexers 2. 1 Il.

Description

Редактор Е.ПаппEditor E. Papp

Составитель И.КарповаCompiled by I. Karpov

Техред М.Ходанич Корректор. М.МаксимишинецTehred M. Khodanich Proofreader. M.Maksimishinets

Заказ 280Order 280

Тираж 570Circulation 570

ВНИИПИ Государственного комитета по изобретени м и открыти м при ГКНТ СССР 113035, Москва, Ж-35, Раушска наб., д. 4/5VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5

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Claims

Claim

An information input device comprising a keyboard, multiplexers, a pulse generator, a counter, first and second AND elements, a group of AND elements, an OR element, a NOT element, a trigger, an output of a pulse generator is connected to the first input of the first AND element, the output of which is connected to the counting input a counter whose outputs are connected to the address inputs of the first multiplexer, the information inputs of which are connected to the outputs of the group of high-order bits of the keyboard, the address inputs of each subsequent, except the last, multiplexer with are identical with all but the oldest address inputs of the previous multiplexer, and the address input of the last multiplexer is connected to the address input of the previous multiplexer, the information inputs of each subsequent multiplexer are connected to the corresponding outputs of the group of the least significant bits of the keyboard, the output of which is connected with the first input of the OR element, the outputs of the multiplex of litter are connected to the inputs of the second AND element, the output of which is connected to the second input of the OR element and the input of the element NOT, the outputs of which are connected to the inputs of the reset 20s and the trigger settings, the inverse output of which is the gate output of the device, and the direct output is connected to the second input of the first element And, the output of the low order 25 of the counter is the information output of the low order of the device, and the outputs of the highest bits of the counter are connected to the first inputs of elements AND groups, the second inputs of which are connected to the output of the last multiplexer, the output of the penultimate multiplexer is connected to the third inputs of elements AND groups, except the first, and the output Each previous multiplexer, in addition to the first and second, is connected to other inputs of the elements of the AND group, except for the first, characterized in that, in order to improve the performance of the device, a group of OR elements and a group of NOT elements are entered into it, the inputs of which are connected to the outputs of the counter, and the outputs of the elements of the NOT group, except the last, are connected to the first inputs of the corresponding elements of the OR group, the second inputs of which are connected to the outputs of the corresponding elements of the AND group, and the outputs of the elements of the OR group together in the output last NOT a member of the group are data outputs most significant bits of the device.