SU1538175A1 - Antilogarithm digital-to-analog converter - Google Patents

Abstract

The invention relates to a converter technique, in particular to converters of the digital form of information into analog, and can be used in information measuring and control devices and systems. The purpose of the invention is to improve the accuracy of the conversion. An anti-log DAC contains several attenuation stages performed on multiplying D / A converters, an analog multiplexer, a voltage follower and a code converter consisting of several AND elements and switches. Accuracy improvement is achieved by grouping the attenuation stages and using an analog multiplexer to eliminate errors and noises that do not work for certain codes of the upper attenuation stages, as well as using several DACs of the same type in each attenuation stage to reduce random conversion errors. 4 il.

Description

The invention relates to a converter technique, in particular to converters of the digital form of information into analog, and can be used as part of logarithmic analog-to-digital converters, as well as in information-measuring and control devices and systems.

The purpose of the invention is to improve the accuracy of the conversion.

FIG. 1 shows a flowchart of a converter; in fig. 2 - functional diagram of the attenuation cascade; in fig. 3 is a functional diagram of the code converter in FIG. 4 - plots of random error | 5 (attenuation cascade versus attenuation value A} of the cascade with a different number S; graphs of a digital-to-analog converter (DAC)).

The anti-log DAC contains an input bus 1 n-bit digital code (bits 14.1 g, ..., 1), p stages 2 attenuation, analog multiplexer 3, repeater 4 voltage, analog output 5, decoder 6, analog input 7, bus 8 logical units.

The entire set of p decay stages z is divided into m groups (mЈn), each of which contains one or more series-connected 2 decay stages, with the output of the cascade being in the j-n group (, 2 ,, .., m) last, connected to (jH) -M analog signal input

but

sl so oo

01

Multiplexer 3, whose signaling signal is connected to an analogue loop 7 of the device.

Each i-th attenuation stage (Fig. 2) consists of one or several (S;) p-decoupling multiplying DACs 9,, ..., 9К, connected in series by an analog signal. . ., 9e; and has an analog input (0), an ana / a (south) output 11, a first control stroke 12 connected to the i-th discharge bus 1 of the device and a second control input 13 connected to a stroke 8 of a logical unit. The digital inputs of each DAC 9 are divided into groups with a total weight o of bits that are related to them and N correspondingly (, 2, ..., n;, 2,. „, S |). All digital inputs of a digital group DAC are connected to the first control input of the 12th decay stage, i all digital inputs of the second group are Ј the second control input 3 of cassor 3. The second input j-ro of digital switch 14 is fed with a fixed code Na (j4- ,}, corresponding to the inclusion of (j +) - ro channel of analog multiplexer 3.

Each j-th element And 5 has the number of inputs corresponding to the number of cascades 2 in the j-th group

Q decay stages (FIG. 1), the designation of these inputs in FIG. 3 (T (, ..., 1P) coincides with the designation of the corresponding control inputs of the anti-log DAC in Fig. 1.

5When on all bits the input

bus 1 there are logical units (this case corresponds to zero attenuation of the device), the outputs of all elements 15 and 15 also have Q logical logical lines, while the code from its first input passes to the output of each switch on the switch,

so, output 17 will be code Na ,, a

about

in multiplexer 3 is enabled per

kada, and therefore with the bus 8 logical 25 channel. The analog signal is in this unit of the device.

The decoder 6 (Fig. 3) contains m digital switches 14 ,,, 14, ...,

15,

14, ng elements and 15 ,,

 2 ..

15t, input bus 16 n-bit yes, field of graying INUY to the input bus 1 antchpogar fmichesky DAC, output circuit 17 and (t + 1) digital, ix tires 18 j, 18l, .. "., 18 t + , assignments of fixed members (sonstants N, s ..., Md (m + l, 15

Antilog DAC works as follows.

The input bus 1 receives the digital code B, defined by bits L; °,

B 2; -Bis

i l

where V. - weights of bits,

40

passes from the input bus 7 to the output 5 of the device, I mknu all-cascades 2 attenuation,

s

When a logical nout appears on any of the inputs of the i-th group, the j-th switch connects the code Nq, "l,

In this case, the multiplexer 3 connects through the (j + 1) -th channel the repeater 4 input (ky. $) to the output of the j-th group of stages 2 attenuation.

When the device is operated with a voltage of one polarity, the number of attenuation cascades in the band should be even to exclude signal inversion.

In the cascade 2-1, the decay bit b; B code goes to the first group

In the cascade 2-1, the decay bit b; B code goes to the first group

Analog input 7 is supplied via the Digital inputs of all DAC 9 cascade,

having total weights N (q.tI, 2,.,., S-). Attenuation k-ro DAC 9 in

this voltage V. Each bit b; controls its Jth cascade 2 decays of the anti-log DAC., sets it to one of 2 states: to the zero decay state or to the fixed decay state A ;. The input code B from bus 1 simultaneously arrives at the input 16 of the decoder 6, the output 17 of which controls the state of multiplexer 3. The first input of the first digital switch 14 is fed with a fixed code N, corresponding to the inclusion of the first channel of the analog multiplex 1 stage 2 view) -, Uoge S SliJLS & JL

(ABOUT

50

55

-, KH, J- «-. & AN

where about - scale factor; and - the base of the logarithm;

W, -1

 - total weight of all q razr to

DAC 9,

Since b {takes only two values: 0 or 1, expression (1) can be written as

A; K (b;) b; - A; K, where b; - bit inversion.

out channel. Analog signal at the same time

passes from the input bus 7 to the output 5 of the device, I mknu all-cascades 2 attenuation,

s

When a logical nout appears on any of the inputs of the i-th group, the j-th switch connects the code Nq, "l,

In this case, the multiplexer 3 connects through the (j + 1) -th channel the repeater 4 input (ky. $) to the output of the j-th group of stages 2 attenuation.

When the device is operated with a voltage of one polarity, the number of attenuation cascades in the band should be even to exclude signal inversion.

In the cascade 2-1, the decay bit b; B code goes to the first group

Digital inputs of all DAC 9 cascade,

1st stage 2 attenuation has the form) -, Uoge S SliJLS & JL

(ABOUT

0

five

-, KH, J- «-. & AN

where about - scale factor; and - the base of the logarithm;

W, -1

 - total weight of all q bits

DAC 9,

Since b {accepts only two values: 0 or 1, expression (1) can be written as

A; K (b;) b; - A; K, where b; - bit inversion.

 TO

B; A ;, (2)

The decay of the i-ro cascade, equal to A; (b;) b; A; K b; BUT;

takes two values: when the attenuation is zero, when the attenuation is maximum and equal to A.

Choose

BUT; , (3) where & - the required resolution of the anti-log DAC.

Then from (2) the total attenuation of the device

(b;) SB,

Where

AT

B In the same way, the attenuation of an anti-log DAC linearly depends on the input code B. Since the attenuation is associated with a logarithmic dependence with the transmission coefficient of the device Ki,

T v

you are v6x.

Ј6

;.

those. The dependence of the output voltage of the device on the input code is an exponential (anti-log) function.

Calculate the weights of N (4 - ,, H; cdl of each DAC 9 in cascades 2, providing the required attenuation (3) of each cascade, and weatherize the improvement in conversion error due to the use of several DACs 9 in cascades 2, and also we give a justification for improving the accuracy of the anti-log DAC due to the introduction of the plexor 3 multitas.

First, we consider several DACs 9 in cascade 2. The left-hand side of expression (4) can be broken down into terms in the pro- gramme. However, to reduce the random error of 1st stage 2, it is necessary to strive for the most even distribution of A between the DACs included in the cascade, i.e.

Then the desired weight is d; s7

N value

N,

(five)

(6)

, 2; k due to the fact that A; can be set continuously and arbitrarily, is continuous. Physically implementable solutions are the natural values of N K si ;;

"to

Denote N

natural

NUMBER

Case. Should accept

N

2.K

(7)

Case. As a zero approximation, we take (7).

In this case, the attenuation of the k-no DAC in the i-th stage will be

A.-siloga, (S)

and attenuation 1st

about cascade 2

Well

15

20

 - /

BUT; ZA; K. (9)

Ksl

The magnitude of the partial systematic error of the transformation due to the discreteness of the formation of logarithmic levels (the error of the method) will be

fljiH 1st Cascade 2

D; A; -A ;. For D; fair assessment

(S) (I)

25

0.5

M; k / t „" "s 8"

N,

35

S; oO

(12)

The mechanism of reducing the systematic 3Q error with increasing S; due to two factors.

The first factor follows from the nature of dependence (12). To reduce the error, it is necessary with increasing A; increase S; .

The second factor. With S, i 2, mutual error compensation (10) is possible by specifying the zero approximation (7) as follows:

40NfelK-NziK qK,

where ± 1; ± 2, ... and: "H2.

In this case, due to the asymmetric dependence (12) relative to the point of the given damping A (it is possible to choose such q: that the errors (10) are largely compensated.

Random error / W. A single DAC, expressed in logarithmic decay units, due to the presence of bias and non-linearity, is expressed by the formula

| i; K oiloga (1+ AN

45

50

N,

.-8e

) 03)

where UNn is the error taking into account nonlinearity and offset, expressed in units of the least significant bit (EMP).

Random errors of different DAC instances included in the i-th stage,

It is possible with some approximation to be considered independent, so the random error of the 1st stage will be

I4

; (s;, A;) logo (.).

N0.

(14)

Here, too, there is a decrease in the Error with an increase in the case of large A; due to two factors.

The first factor is due to the fact that; in (14) depends on the ratio A; / S (

The second factor, with an increase in the number of DACs in the cascade, the attenuation grows in proportion to S, and the random in jrpeuiHocTb (in relative units) is proportional to 4si.

Therefore, there are such zatuha-} sh A (S ;,, S; 4), in which, with different variants of execution of the 1st kas

garden, different numbers Sj, and S, -2, random errors A; (S ;, A;), ft (S; a А;) are the same p; (S; (, A;) - fJ; (Sja, A, -)) (15)

The joint solution (14) and (15) gives

(sixteen)

Where

s .4t

The graphs of dependence (14)

in FIG. 4 and points are marked on them (16).

Knowing these points, one can make a one-digit choice depending on the required attenuation of stage A: with; () and (2) should be chosen

h 1 - ь, -),

A; (1) and (2) cA; cA; (2) to (3) should be chosen

BUT ; (2) and (3) A; sA; (3) and (4) should be selected, etc.

In this case, the random error of the 1st stage is minimal.

The random error X1 ;: of one DAC due to the error & Ny EMP of the full scale (otherwise called scale error) 9 will be obtained from (13) with

() (17)

The error of the full scale of the 1st cas

kada will be

 m TSHS y; (S;) ciloga. (1+). (16

0

five

0

This error occurs with small attenuations and increases proportionally. With a large attenuation, it can be neglected.

Calculations based on the above ratios show that an anti-log DAC can be implemented using 12-bit DACs 9 with a range of 81, 91 dB, having a systematic conversion error not exceeding one thousandth decibel, random error of 0.03 dB (at the boundary of range) and resolution of 0.01 dB.

The reduction in error due to the introduction of multiplexer 3 is due to the following

In the device, the cascades are connected by an analog signal in order of increasing generated damping A; . In case of small attenuations, a part of the upper stages does not participate in the formation of the resultant attenuation A. By eliminating the error of these stages using the multiplexer 3, the output point of the output voltage is changed.

The error of blocks 3 and 4 is mainly determined by the final resistances of the open channel g and the gthrigorer, the input resistance of the repeater R and the offset of the repeater -all U

d

0

five

five

cm

U see

 (1 + TW

Up-11о8в (Н JL).

The element base makes it easy to do $ n Ј V; ,

If the same amplifiers are used in the attenuation stages 2 and in the repeater 4, the ratio

Pn {b. Therefore, we can assume the error

Any older cascade 2 and blocks 3 and 4 are comparable. Under these assumptions, a decrease in the error of the anti-log converter is provided in the attenuation range O – D / 2, where D is the full range of the device.

Thus, the use of integral DACs in the attenuation stages allows us to reduce the conversion error and improve the resolution of the device, while changing the pickup point of the output voltage depending on the value of the input code

using an analog multiplexer reduces the conversion error in the region of small attenuation

Claims (1)

1. Anti-log digital-to-analog converter containing an n-bit input bus, serially connected on an analog signal of attenuation cascades and a voltage follower, the output of which is connected to the output bus of the converter, an analog input of the first stage of attenuation connected to an analog input An anti-log digital-to-analog converter, characterized in that, in order to increase the conversion accuracy, an analog multiplexer and a decoder are introduced into it, and in anti-log stacks, A digital-to-analog converter is divided into w groups, each of which contains K () serially connected decay stages, and the output of the attenuation stage, which is in the jth group (, 2, ..., m) last, is connected to (JH) -M informational the analog multiplexer input, the first information input of which is connected to the analog input of an anti-log digital-to-analog converter, the output of the analog multiplexer is connected to the repeat input LKG b 1- tpynna jn group 7-7  1st &. input code f fie-t the voltage body, the first control input of each 1st stage (, 2, ..., p) of the attenuation is connected to the i-th input of the decoder and connected to the input of the 1st bit of the input bus of the anti-log D / A converter, the second control input 1 th decay stage is connected to the bus of a logical unit, the digital output of the decoder is connected to the control input of the analog multiplexer. 2 "Converter according to claim 1, wherein the topic is to increase the accuracy of the conversion; therein each stage attenuation comprises one or more serially connected analog signal multiplying digital to analog converters, the analog input of the first digital to analog converter stage attenuation connected to the analog input stage, an analog output of the last DAC stage attenuation connected to the analog output stage and the digital inputs of each multiplying digital to analog the converter is divided into two groups, with all the digital inputs of the first group combined You are connected to the first control input of the cascade, all the digital inputs of the second group are combined and connected to the second control input of the attenuation cascade. Swwf i-s -f- (" Hp MJLjKl. Group , A7 A1, b) .and ha eurplv