SU1536422A1 - Device for reception and transmission of information - Google Patents

Abstract

The invention relates to the field of receiving and transmitting information and can be used to transmit and receive information transmitted in binary code in systems with a large number of receivers and transmitters operating in the same communication channel. The aim of the invention is to increase the reliability of the reception and transmission of information. The device contains a receiver 1, selector unit 2, selector 3 zero, first 4, second 5, third 6, fourth 7, fifth 8 OR elements, clock pulse generator 9, first 10, second 11, third 12, fourth 13, fifth 14, sixth 15, seventh 16 And elements, shift register 17, comparison block 18, memory block 19, encoder 20, decoder 21, first 22 and second 23 D-flip-flops, first 24 and second 25 RS-flip-flops, information driver 26 , counter 27, delay element 28, unit code generator 29, zero code generator 30, transmitter 31, communication channel 32, information sources 33, inform 34, clock 35 outputs, output "Start" 36 and output "Stop" 37. The device allows increasing the reliability of the transmitted information by synchronizing the received information message with clock pulses of its own generator, using the start and end characteristics in the message structure . 1 il.

Description

31536

nergy 7, fifth 8 elements OR, shaper 9 clocks, first 10, second 11, third 12, fourth 13, fifth 14, sixth 15 and seventh 16 elements AND, shift register 17, comparison block 18, memory block 19 , encoder 20, decoder 21, first 22 and second 23 D-flip-flops, first 24 and Shoroy 25 RS-flip-flops, information generator 26, counter 27, delay element 28, unit code generator 29, zero code generator 30,

transmitter 31, communication channel 32, information sources 33, information 34 and clock outputs 35, output 36 Start and exit 37 Stop. The device allows, by synchronizing the received information message with the clock pulses of its own generator, by using in the message structure the Start and End code characteristics to increase the reliability of the transmitted information. 1 il.

The invention relates to the transmission and reception of information and can be used to receive and transmit information transmitted in binary code in systems with a large number of receivers and transmitters operating in the same communication channel.

The purpose of the invention is to increase the reliability of the reception and transmission of an information message.

The drawing shows a functional diagram of the device.

The device contains receiver 1, selector unit 2, selector 3 zero, first to fifth 4-8 elements OR, shaper 9 clocks, first to seventh 10-16 elements I. shift register 17, block 18 comparison, memory block 19 TI, encoder 20, descrambler 21, first 22 and second 23 D-flip-flops, first 24 and second 25 RS-flip-flops, information generator 26, counters 27, delay element 28, unit code driver 29, transmitter of code zero 30, transmitter 31, communication channel 32, information source 33, information output 34, clock output 35, start output 36 and exit 37 Stop .

The device interacts with the central point as follows.

From the central point, the subscriber who has this device installed receives a parcel containing the code sign of the subscriber. After receiving its code K-raer one sign, the subscriber, having entered into a dialogue, notifies the central point of readiness for work by sending a receipt message via the communication channel.

five

0 5

0

Q 5

0

five

then an information message is transmitted from the central point, the first To bits of which contain the Start code characteristic, and the last - the End code attribute, after receiving which the device stops receiving the message from the central point and notifies it about the end of the dialogue with it by sending a receipt message through the channel connection.

The device works as follows.

After turning on the power, the device is reset (setting circuit not shown), in which the D-flip-flops 22 and 23, the RS-flip-flops 24 and 25, the shift register 17 and the counter 27 are in the zero state. In the absence of any signals in the communication channel, there are no reset signals on the R-output of the counter 27, and the counter 27 generates signals at certain time intervals, which through the third 6 and fourth 7 OR elements also set the device to its initial state.

In the initial state, zero signals are transmitted to the inputs of the decoder 21 from the first 22 and second 23 D-flip-flops, causing the output signal only on the first output of the decoder 21, under the action of which the output of the encoder 20 generates an n-parallel code transmitted to the address bus of the block 19 memory. From the memory block 19 with this address, the K-peer d- is selected for the subscriber’s code feature information and is set at the second inputs of the comparison unit 18.

From the communication channel, the information message is received by receiver 1 by selector unit 2, by selector 3 zero, and transmitted to the information input of shift register 17 and to the first element OR 4, designed to generate clock pulses that come from the output of the first OR element to the driver 9 clock pulses, where they are tied 1 and to the signals of the own generator, located in the information generator 26. The clock pulses from the output of the imaging unit 9 clock pulses through the second element And 11 are transmitted to the clock input of the shift register 17 and record the information transmitted to its information input from the output of the selector 2 units. Information from the output of the shift register 17 is transmitted to the first inputs of the comparison unit 18, where it is compared with the information transmitted from the memory unit 19. When finding its code feature, the comparison unit 18 is polled by the first D-trigger 22, whose information input is connected to the output of the comparison unit 18 via the first element AND 10, and the clock through the delay element 23 to the clock input of the shift register. When B is written, the shift register 17 of its K-bit of the first code sign by the delayed clock pulse, the first D-flip-flop 22 and the first RS-flip-flop 24 are set to one, and the signal from the inverse output of the RS flip-flop 24n to the second input of the second element And 11, the flow of information into the device is blocked, a signal from the output of PS flip-flop 24 through the fifth element OR operation of the unit code generator 29 and the zero code generator 30 is enabled, information generator 26 is released and, through the second element OR 5, is forcibly held In the zero state, the counter 27 single signal from the output of the first D-flip-flop 22 causes the output signal on the second output of the decoder 21, according to which the encoder 20 forms the cell address of the memory block 19, from which the second inputs of the block are extracted and installed

18 Comparisons.

code sign

about 10

15

20

After starting, the control input in the information generator 26 converts the parallel code from the information source 33 into a serial one and sends ei 0 through the information output to the inputs of the unit code generator 29 and the zero code generator 30, the output of which is the code message signals confirming the subscriber’s readiness to work with the central point, they are transmitted through the transmitter 31 to the communication channel. After the last character of the receipt code is transmitted, a signal appears through the control output of the information generator 26, which through the fourth element OR 7 sets the shift register 17 and the first RS-tripper 24 to the zero state, while allowing information to be written to the shift register 17.

After the information message with the code 25 sign starts to be written to the shift register 17, a single signal appears at the output of the comparison block 18, allowing passage through the third And 12 element of the delayed clock pulse to the Start output and to the clock input of the second D-flip-flop 23.

The Start signal is transmitted to the subscriber, notifying him of the start of the transmission of an information message for him, and translates the second D-flip-flop 23 into one state, the output of which opens the sixth 15th and seventh 16 And elements to transmit through them and through the informational 34 and clock 35 outputs subscriber informational message. In addition, the output from the second D-flip-flop 23 is transmitted to the second information input of the decoder 21, which causes the output of the d5 signal to appear on its third output, through which the encoder 20 generates the address of the cell 19 of the memory, from which the second the inputs of the block 18 comparison code feature End.

At the end of the transmission of the information message, the End code code is transmitted over the communication channel, after recording which in the register 17 of the SD register at the output of the comparison unit 18 a single link appears allowing the passage through the fourth element 13 of the delayed tact of the output pulse 37 Stop and S-input of the second RS-flip-flop 25.

thirty

35

40

50

55

7153

The Stop signal is transmitted to the subscriber, notifying him of the end of the transmission for his message, and translates into a single state the second RS flip-flop 25, the output signal of which sets the zero state — the n-dimensional D flip-flop 22 and starts up the 26 information for transmission over the channel connection of the receipt signal, and the signal from its inverse output prohibits reception of the message in the shift register 17.

At the end of the receipt of the receipt of the message with the signal from the control output of the information generator 26, the entire device is reset to the initial state as described.

If after receiving your code

When the indication signal is transmitted to the communication channel and the information message is not received for a long time, the device is reset to the initial state by a signal from the output of the counter 27 through the third 6 and fourth 7 OR elements. Similarly, the device exits the emergency situation even when the code sign End is not found in the incoming information message for a long time.

Thus, the device provides a high reliable reception and transmission of the informative message by synchronizing the received message symbols and the generator signals of the information generator 26, interrogating the result of the received message with information from the memory block 19 with each clock pulse, as well as processing informational message, in the structure of which the beginning and end coding features are introduced.

Claims (1)

Invention Formula A device for receiving and transmitting information containing a receiver, whose input is combined with the transmitter output and connected to the communication channel, the receiver output is connected to the inputs of the unit selector and the zero selector, the output of the zero selector is connected to the first input of the first OR element, the output of which is connected to the first log in 0 50 , Q 5 0 five eight the driver of clock pulses, the output of the unit selector is connected to the second input of the first OR element and to the information input of the shift register, whose outputs are connected to the first inputs of the comparator unit, the second inputs of which are connected to the outputs of the memory unit, the output of the comparator unit is connected to the first input of the first element And, the second element And, the output of which is connected to the clock input of the shift register, the information driver, the first inputs of which are connected to information sources, the first output of the information generator connected to the first inputs of the unit code generator and the zero code generator, the outputs of which are connected to the transmitter inputs, the second output of the information generator, is connected to the first input of the counter and to the second inputs of the unit code generator and the zero code generator, the second OR element, characterized in that In order to increase the reliability of the reception and transmission of information, the third, fourth and fifth elements of OR, from the third to the seventh elements of AND, the coder, the decoder, the first and second D-triggers, the first and second PS-triggers, and the delay time, the output of the comparison unit is connected to the first inputs of the third and fourth elements And, the output of the second element And connected to the first inputs of the fifth and sixth elements And through the delay element to the second inputs of the third and fourth elements And to the clock input of the first D- trigger, the inverse output of which is connected to the second inputs of the first and fifth elements of AND, the output of the latter is connected to the first input of the second element OR, the output of which is connected to the second input of the counter, the output of which is connected to the first inputs of the third and the fourth element OR, the output of the first element I is connected to the information input of the first D-flip-flop and the S-input of the first RS-flip-flop, the output of the third element OR is connected to the R-input of the first D-flip-flop, the forward output of which is connected to the first input to the third input of the third element And, the output of which is connected to the clock input of the second D-flip-flop and is the device Start output, the direct output of the second D-flip-flop is connected to the second input of the decoder, to the third input of the fourth element And, the second input of the sixth and the first the input of the seventh And elements, the outputs of the sixth and seventh And elements are respectively the clock and information outputs of the device, the output of the fourth element And is connected to the S input of the second RS flip-flop and J is the output of the Stop device, the direct output of the first RS flip-flop is connected to the first input of the fifth element OR, the output of which is connected to the second inputs of the second element OR and the form | And, the inverse output of the information generator, to the third inputs of the unit code and zero codes, the inverse output of the first RS-trnger is connected to the second input of the second element, And the forward output is 2Q of the RSO trigger and the second input nth elements The D-flip-flop is connected to the fourth input of the third element I, the information input of the second D-flip-flop is connected to the input of a single potential, the output of the decoder is connected via coder1 to the input of the memory unit. OR, the inverse output of the second RS trigger is connected to the third input of the second element AND, the second output of the information generator is connected to the second input of the clock generator, the third output of the information generator is connected to the second input of the fourth element OR, the output of which is connected to the combined R inputs of the shift register the first and second PS-flip-flops and the second D-flip-flop, the output of the unit selector is connected to the second input of the seventh element And, the inverse output of the second The D-flip-flop is connected to the fourth input of the third element I, the information input of the second D-flip-flop is connected to the input of a single potential, the output of the decoder is connected via the encoder 1 to the input of the memory unit.