SU1534752A1 - Device for digital amplitude demodulation - Google Patents

Abstract

The invention relates to the field of pulsed technology and can be used in information transmission and processing systems with pulse amplitude coding. The purpose of the invention is to increase the reliability of demodulation and broaden the dynamic range of demodulated signals by generating a threshold that follows the middle of the decision zone about the amplitude of the signal. It is achieved by introducing into the device the registers 9, 10, the inverter 15, the multiplier 13 and the adder 11. The device also contains an extremum selection unit 1, an analog-to-digital converter 2, registers 3, 4, 7, 8, a subtracting unit 5, a block 6 for determining the maximum differential, block 14 versus threshold. 2 Il.

Description

The invention relates to pulsed technology and can be used in information transmission and processing systems with pulse-amplitude coding g.

The aim of the invention is to increase the reliability of demodulation and the expansion of the dynamic range of demodulated signals due to the development of a threshold 'tracking' the middle of the decision area on the signal amplitude.

In FIG. 1 shows a functional diagram of a device for digital am-15 digital demodulation; Fig. 2 is a graph of the input signal.

'The device contains an extremum selection block 1, an analog-to-digital converter 2, registers 3 and 4, a subtracting block 5, a maximum differential block 6, registers · 7τ10, an adder 11, and multipliers 12 and. 13, a block 14 for comparison with a threshold and an inverter 15, while connecting in series 25 an extremum selection block 1, an analog-to-digital converter 2, registers 3 and 4, the outputs of which are connected to the inputs of the subtracting block 5, whose input is connected through 30 therefore, the maximum differential determination unit 6, registers 7 and 8 are connected to the second input of the adder 11, the output of which is connected to the inputs of the multipliers 13 and 12, the output of the latter through register 10 is connected to the first input of the adder 11, the third input of which is connected to the register output 9, entrance to is connected to the output of the register 7 and the first input. up to the comparison unit 14 with a threshold, the second input of which is connected to the output of the multiplier 13, and the output is connected to the output bus, the control input of the register 8 and through the inverter 15 to the control 45 of the input of the register 9.

The device operates as follows.

An analog two-level signal (Fig. 2) is supplied to an extremum selection unit 1, which, in the simplest case, is a differentiating device and an analogue sample-storage cell, which is recorded in gg by a signal from a differentiating device.

The analog-to-digital converter 2i converts analog-to-code, ¹ and all further processing takes place digitally. The ADC is launched and the digital circuits are synchronized according to the signals of the differentiating device in block 1 of the extremum selection.

The code of the current extremum is stored in register 3. In the register 4, the code of the previous extremum is stored. The subtracting unit 5 generates the absolute value of the difference of the values stored in registers 3 and 4, which is supplied to the block b for determining the maximum difference.

Block 6 determining the maximum difference consists of a memory register and a code comparison circuit. The code of the current extrema difference coming from the subtracting block 5 is compared with the code of the previous difference stored in the memory register of block 6 for determining the maximum difference. If the current code is greater than or equal to the previous one, the analysis continues, otherwise, a decision is made to determine the maximum difference (FIG. 2), and its code goes to register 7, in which the current maximum difference compared with the threshold in block 14 is stored, The threshold is developed in accordance with a decisive rule of the form u + (0 where ft; «(U ;. _n + U ;. _k ) / 2; n _# k ¥ 0TN U; = | U (t; _,) - U (t _:) |,

- non-trivial statistics corresponding to the maximum difference in signal sending;

'~ location of the global extremes of the parcel;

- statistics of the high level signal (n is the number of low level signals between the analyzed one. 1 “M signal and the last high level signal); ·

- statistics of the low level signal (k is the number of high level signals between the ith signal and the last low level signal).

the threshold is calculated using exponential smoothing with a coefficient of 0.5, which eliminates the influence of impulse noise due to where

V 1

taking into account the history from the moment the device was turned on. The code from register 7 is written to register 8 when demodulating a high-level signal, when demodulating a low-level signal, code from register 7- is written to register 9, for which the output of the comparison unit 14 with a threshold is connected directly to the control input of register 8, and to the control input of the register 9 - through the inverter 15.

Thus, in register 8 the current value of the high-level signal statistics code is stored in register 9; the current value of the low-level signal statistics code (U; _ _k ) is stored.

The right side of expression (1) can be transformed as follows:

< ^{ϋ ί} -η ^{+ U} i'-k ⁺² ^ - << ² >

In accordance with expression (2), the current threshold is generated by summing the codes U ;. the code of the doubled previous threshold 2 ^At A; _ ₁ using the adder 11 and multiplying the result by a factor of 0.25 by the multiplier 13. The doubled value of the exponentially smoothed previous threshold is obtained by multiplying the code at the output of the adder I 1 that occurs when i-1- nd Parcels, by a factor of 0.5 using a multiplier 12. The code of the previous doubled threshold is stored in register 10, From the output of the multiplier 13, a threshold that monitors the middle of the decision area is fed to the second input of the comparison unit 14 with a threshold where it is compared code U ;, current statistics stored in the register 7.

A demodulated signal, which is a serial digital code, is obtained at the output of the threshold comparison unit 14.

When the device is turned on, all the registers contained in it are automatically reset to zero, and a logical unit is written to the higher bits of registers 8–10, which ensures the correct further operation of the device.

Thus, the introduction into the device of digital amplitude demodulation of two registers, an adder, is clever5. the resident and the inverter allows eliminating the influence of pulsed noise by taking into account the signal history from the moment the device was turned on, which, in turn, reduces the probability of demodulation of the input signal by several times, and evens out the probabilities of erroneous demodulation of high and low level signals by generating a threshold monitoring the 15th middle of the decision-making zone when changing the ratio of levels, which for a given reliability of demodulation is equivalent to expanding the dynamic range of demodulated sig2 0 catch.

Claims (1)

Claim A device for digital amplitude25 demodulation, which contains an extremum selection block connected in series, an analog-to-digital converter, first and second registers, the outputs of which are connected to the inputs of the subtracting block, to the output of which a maximum difference determination block, a third register, and a fourth register are connected in series the control input of which 35 is connected to the output bus and the output of the comparison unit with a threshold, the first input of which is connected to the output of the third register, and the second input to the output the first multiplier, with 40 hours, in order to increase the reliability and expand the dynamic range of demodulated signals, the fifth and sixth registers, 45 inverters, the second multiplier and adder, the output of which connected to the input of the first multiplier and through a second multiplier and the fifth register connected in series to its first 50 input, the second input to the output of the fourth register, and the third input to the output of the sixth register, the input of which is connected to the output of the third register, and the control input - with the output of the inverter input coupled to the output bus.