RU2017337C1 - Delay-pulse pseudorandom noise discriminator - Google Patents

Abstract

FIELD: electrical communication, radio engineering. SUBSTANCE: discriminator has low-pass filter 1, first and second two-threshold circuit elements 2,6, first, second, third, and fourth delay circuit elements 3,8,10,15, first and second multiplier units 4,19, majority function unit 5, pulse counter 7, frequency-shift register 9, switching unit 11, pseudorandom noise generator 12, clock-pulse generator 13, correlation device 14, threshold circuit element 16, adder 17, additional delay circuit element 18, attenuator 20. EFFECT: increased noise stability. 2 dwg

Description

 The invention relates to telecommunications and radio engineering and can be used in information transmission and ranging systems.

 The purpose of the invention is to increase noise immunity.

 In FIG. 1 shows a structural electrical diagram of a device for searching a pseudo-noise signal (PSH) by delay; figure 2 is an embodiment of a second two-threshold block.

 The delay PNS search device comprises a low-pass filter (LPF) 1, a first two-threshold block (DPB) 2, a first delay line 3, a first block of multipliers 4, a majority block 5, a second two-threshold block 6, a pulse counter 7, a second delay line 8, shift register 9, third delay line 10, switching unit 11, PShS generator 12, clock generator 13 (TI), correlator 14, fourth delay line 15, threshold block 16, adder 17, additional delay line (LZ) 18, second block multipliers 19, attenuator 20.

=

^Z; на втором выходе будет 1, если напряжение на входе больше верхнего порога, и 0, если меньше

Первый ДПБ 2 построен на компараторах так, что, если напряжение на входе больше верхнего порога, то на выходе +1, если меньше нижнего порога, то -1, а если находится в пределах между верхним и нижним порогами, то 0:
U_вых=

Мажоритарный блок 5 представляет собой сумматор.The second two-threshold block (DPB) 6 contains the first and second comparators 21 and 22, the inverter 23 and the OR element 24. The voltage at the first output of the DPB 6 will be +1 if the input voltage is greater than the upper or lower lower threshold, and 0 if the input voltage is between the upper and lower thresholds:
U

=

^Z; the second output will be 1 if the input voltage is greater than the upper threshold, and 0 if less

The first DPB 2 is built on comparators so that if the input voltage is greater than the upper threshold, then the output is +1, if it is less than the lower threshold, then -1, and if it is between the upper and lower thresholds, then 0:
U _out =

The majority block 5 is an adder.

 The counter 7 pulses is a summing counter with a capacity of n. It counts the number of consecutive +1 characters, and when this number becomes equal to n, an impulse appears at the output, and the counter is reset to zero. When entering the input of the counter of character 0, the counter is reset.

 Attenuator 20 is a linear circuit with a transmission coefficient of less than one.

 The search device PNS on the delay works as follows.

C

, где C_i - символы ПШС;
α_i - коэффициенты порождающего полинома ПШС, определяющие обратные связи регистра сдвига, формирующего ПШС (α_i∈{0,1}).The input PNS is fed to the input of the low-pass filter 1, which acts as a filter, consistent with a single symbol of the PNS. From the output of the low-pass filter 1, the signal enters through the adder 17 to the input of the additional LZ 18. The PShS symbol from the taps of the LZ 18 is fed to the inputs of the second block 19 of multipliers. In block 19 of the multipliers, the next PSH symbol is predicted from the previous ones in accordance with the algorithm:
C _j =

C

where C _i - the characters of the PShS;
α _i are the coefficients of the generating PNS polynomial, which determine the feedbacks of the shift register forming the PNS (α _i ∈ {0,1}).

Raising to the power α _{i is} carried out by the presence (α _i = 1) or absence (α _i = 0) of the connection of the corresponding branch LZ 18 with the corresponding input of the second block of multipliers 19. The attenuator 20 is designed to prevent self-excitation. From the output of the second block of multipliers 19, the predicted PSH symbol through the attenuator 20 enters the adder 17, where it is added to the received symbol of the PShS. If the PNS symbol is received correctly, then at the output of the adder 17 its amplitude will be greater than at the input, and if distorted, then less.

осуществляющих оценку символа a_i через другие символы r сигнала. При этом, если хотя бы один из символов, в входящих в данные проверочные соотношения, является сомнительным, т.е. равным 0, то на соответствующем выходе первого блока 4 перемножителей также будет 0. Таким образом исключается влияние на оценку ненадежных символов.From the output of the adder 17, the next symbol is fed to the input of an additional LZ 18, as well as to the input of the first DPB 2, the output of which the signal is a sequence of symbols +1, 0, -1, and 0 are symbols that do not exceed any of the thresholds of the first DPB 2, i.e. characters that are unlikely to be correctly recognized. From the output of the first DPB 2, the signal goes to the input of the first LZ 3, in which the system of check relations of the form is implemented in the first block 4 of multipliers

evaluating the symbol a _i through other symbols r of the signal. Moreover, if at least one of the symbols in the verification relations included in the data is doubtful, i.e. equal to 0, then the corresponding output of the first block of 4 multipliers will also be 0. Thus, the influence on the evaluation of unreliable characters is excluded.

 At the output of the majority block 5 there will be a signal of positive polarity if there are more +1 symbols at its input than -1 symbols, and a signal of negative polarity if the opposite relationship takes place. The zero signal at the output of the majority block 5 will be only if at its input the number of characters +1 and -1 is equal, and the rest are zeros.

 At the first output of the second DPB 6, the signal is a sequence of ones and zeros, and the units are estimates formed only by reliable symbols (correspond to levels +1 and -1 at the output of majority block 5). Using counter 7, a segment is selected from n symbols of the sequence 1 and 0 at the second output of the second DPB 6, which does not contain estimates generated by an unreliable symbol.

 In the shift register 9, from the second output of the second DPB 6, a sequence of ones and zeros is written, and if the segment is correctly selected, level 0 corresponds to level -1 at the output of the majority block 5. As soon as such a segment is recorded in register 9, the pulse from counter 7 allows the recording of contents register 9 in the generator 12 PSH through block 11 switching. The third LZ 10 delays the input signal of the register 9 with the aim of matching it in time with a signal that allows the recording of the selected segment in the generator 12 PNS.

 The operation of the register 9, counter 7 and generator 12 ПСС is synchronized by pulses of generator 13. To check the correct synchronism of the received ПСС and generated in the search device ПСС by the delay, these signals are fed to the correlator 14. The received ПСС is delayed by the fourth ЛЗ 15 during the processing of the input signal in the corresponding blocks .

 To prevent a possible situation of writing a new segment to the PNS generator 12, the pulse from the counter 7 is delayed by the second LZ 8 for the period of the verification check in the correlator 14. If, after processing the input signal, the voltage at the output of the correlator 14 exceeds the threshold value, then the pulse appears at the output of the threshold block 16, which prohibits the recording of a new initial state in the PNA generator 12 through the switching unit 11 and shows that the delay signal search was successful. If the threshold is not exceeded in the threshold block 16, then when the next pulse arrives from the counter 7 in the generator 12 ПСС the new state is recorded.

Claims (1)

 DEVICE FOR SEARCHING A PSEUD NOISE BY DELAY containing a first delay line, a correlator and a threshold block, a low-pass filter, the input of which is connected to the input of the first delay line and is the input of the device, as well as the first two-threshold block, the second delay line, and the multiplier block , majority block, second two-threshold block, third delay line, shift register, switching block and pseudo noise signal generator (PSH), the output of which is connected to another input correlator, the second output of the second two-threshold block is connected through a sequentially connected pulse counter and the fourth delay line to the enable input of the switching unit, the inhibitory input of which is connected to the output of the threshold block, the clock inputs of the PShS generator, shift register and pulse counter connected to each other and to the output of the generator clock pulses, characterized in that, in order to increase noise immunity, an adder is inserted between the output of the low-pass filter and the input of the first two-threshold block, ezhdu output and the other input of which included additional input serially connected delay line, multipliers and second attenuator unit.

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