SU1534700A1 - Device for control of three-phase adjustable inverter - Google Patents

Abstract

The invention relates to electrical engineering and can be used in the management of converters for asynchronous electric drive systems. The aim of the invention is to reduce the switching losses in the inverter in the process of associated control of the frequency and magnitude of the output voltage. An amplifier 10 with a transmission coefficient equal to two, a key 20, a multi-input adder 21, whose inputs are connected to all outputs of the switching stability unit 15 and to the output terminals of switches 17 and 20, a two-input integrator 22, whose inputs are connected to an adder 21 and an additional source 23, and the outputs are connected to the amplifier 10 and the adder 8. The inverter allows the coupled linear control of the frequency and average value of the output voltage across the half-period to be achieved by the poet pnoy variation time position of one of the fronts (front or back) of each of the output pulses, which reduces the total number of switching power rectifiers especially in high output frequency range of the transducer and reduces the total size of the switching losses. 4 il.

Description

Eyv

and

W

WITH

cn

with

V vl

31534

to two, a key 20, a multi-input adder 219 whose inputs are connected to all and outputs of the block 15 for ensuring commutating stability and to the output terminals of keys 17 and 20, a two-input integrator 22, whose inputs are connected to an adder 21 and an additional source 23, and the outputs are connected to the amplifier 10 and the adder 8. The inverter allows the associated linear frequency control

The invention relates to electrical engineering and can be used to control stand-alone three-phase AND inverters, which are part of asynchronous electric drive systems. The aim of the invention is to reduce switching losses in the inverter in the process of coupled frequency control and output voltage value, provided by reducing the number of additional commutations in the converter power circuit.

Fig. I shows a diagram of the device; FIG. 2 shows the timing diagrams of the inverter operation; in fig. 3 shows an example of the implementation of a pulse shaping unit and a switching resistance unit; FIG. 4 shows timing diagrams of the device operation.

The device contains as nodes a clock pulse generator 1 associated with a three-bit register 2, the outputs of which are connected to the corresponding clock inputs of the logic distributor 3 of control pulses. The generator i signal is also input to the generator 4 of the saw-tooth voltage, the output of which is connected to the inputs of the sensor 5 of the amplitude of the saw-tooth voltage and the pulse duration shaping unit 6. The source 7 of the reference voltage is connected to the positive inputs of adders 8 and 9 and summing amplifier 10 and to the negative inputs of sum-toro 11 and 12. Other positive inputs of adders 8 and 11, 9 and 12 are interconnected and connected to sources 13 and 14, respectively constant voltage. The outputs of these sumi values of the half-period average value of the output voltage carried out by gradual variation of the temporal position of one of the fronts (front or rear) of each of the output pulses, which reduces the total number of switching power gates, especially in the range of increased output frequencies of the converter and leads to a decrease total switching losses. 4 il.

mators are connected to the corresponding inputs of the block 15 for ensuring switching stability. Four respective main outputs of block 15 are connected to the inputs of block 6 for forming pulse durations. Two auxiliary outputs of block 15, the number of which in the general case is equal to n, are connected through the element OR 16 to the control circuit of the key 17,

The other two inputs of block 15 receive signals of auxiliary voltage source 18 and adder 19, respectively, the output of source 18 is connected to the minus input of adder 19, and the positive input of adder 19 is connected to the output of amplitude sensor 5, the output of amplifier 10 is connected via switch 20 to the input unit 6 forming the pulse duration. The odd main outputs of block 15, as well as the output terminals of keys 17 and 20 are connected to the positive inputs of a lot of input adder 21, two negative inputs of which are connected to the even outputs of block 15. The output of adder 21 is connected to the negative input of a two-input integrator 22, to the second positive input which comes from a source of constant voltage source 23. The output of the integrator 22 is connected to the third positive input of the adder 8 and to the second input of the summing amplifier 10. The output of the amplifier 10 is connected to the input of the comparison circuit 24, the second input of which is connected to the output of the adder 19, the output of the comparison circuit 24 is connected to the control circuit of the key 20.

Fig. 2 shows time diagrams for explaining the principle of operation of the device, the duration of which corresponds to the third part of the period of the inverter output voltage curve. The voltages at the outputs of the blocks and components of the control system are hereinafter indicated by indices corresponding to their numerical designations in FIG.

A clock pulse generator 1 periodically starts a sweep sawtooth generator 4, the output signal 114 of which has a constant slope and variable, depending on the pulse frequency of the generator f, an amplitude that continuously detects a sawtooth voltage amplitude 5. In this case, on the period of the input voltage curve, unit 1 generates 12 clock pulses.

The voltages of sources 13 and 14 determine the location of the midpoints of the output pulses at the initial (minimum) output frequency of the converter. The amplitude of the source 7 signal determines the magnitude of the output voltage of the inverter at the initial output frequency. The values of the signals Vn, U, 4 and U7 are determined with a sufficient degree of accuracy from the ratios

2- i 2n + T

U5m

2- I

2 2

- ± -Ј- 2-2 + 1

 T2 + G U5m MU ;;

U "U6m 0.8 U5m;

IT T2P + P GYYTU

 0.04 U

sms

where U 6m is the maximum amplitude of the signal at the output of sensor 5, observed at the lowest output frequency of the converter.

The amplitude of the constant voltage source 23 is determined from the ratio

U

U

w tm 5 t l 9 tt

2p + tgg g i5 ™

The gain of the amplifier 10 K, 0 is equal to two.

The timing diagrams shown in Fig. 2 correspond to the lower frequency range of the inverter when the half-wave of its linear output voltage UAa is formed from the maximum number of pulses equal to eleven at the half-cycle, with minimum durations specified by the value mentioned above. voltage source 7. - Due to the fact that 2, the duration of the central pulses in the half-period in the curve of the linear output voltage 5 is twice the duration of the remaining output equal to each other single pulses.

The formation of the pulses of the output curve of the inverter

Q with this control system is performed by a length-forming unit 6; pulses in moments of equality of the signal generator 4 sweep voltage value voltages, U ,,, U8, and, and U9, taken respectively from the outputs of the amplifier 10 and adders 11,8,12 and 9 transmitted through block 15 to the corresponding the inputs of the formation unit 6,

0 the output of which is indicated in figure 2, as U6.

The main function of unit 15 is to provide a guaranteed amount of inter-switching intervals between adjacent switches of power circuit gates over the entire control range, which ensures the switching stability of the inverter during regulation. This achieves Q with a constant comparison of the lengths of the time intervals between the switching times of the gates with a reference limit value equivalent to

5, the voltage of the auxiliary source 18 and the modification of the algorithm for the further supply of control signals to the block 6 in the case of a reduction in the specified durations below the boundary values. One of the possible options for building interconnected blocks 15 and 6 is shown in FIG.

The main inputs of the block 15 ensure the switching stability, the number of which is generally 2p, are connected to the outputs of the reference adders 8.11, 9 and 12. These input terminals through the keys 25-28 connect 5

yen with the corresponding main outputs of block 15. The outputs of block 15, to which the outputs of amplifiers 8 and 9 are connected, are also connected to the first inputs of comparison circuits 29 and 30, the other two main inputs are connected to adders 31 and 32, the outputs of which, in turn , are connected to the yodes of comparison circuits 33 and 34. The output of the circuit 33 is connected to the control circuit of the key 26, as well as to the input of the element 35, the second input of which is connected with the inverse output of the unit 29 Comparison. The output of the comparison circuit 34 is connected to the control circuit of the key 8 and with the input of the AND 36 element, the second input of which is connected to the inverse output of the comparison circuit 30. The direct Yykhods of circuits 29 and 30 are connected to the control circuits of keys 25 and 27. The second inputs of all comparison circuits of block 15 receive a signal from the output of adder 19. The second inputs of adders 31 and 32 are connected to auxiliary voltage source 18.

The pulse width shaping unit 6 includes Input Comparators 37-41 (the number of Comparators is generally equal to (2p + + 1), the output of which are shapers of short unipolar pulses. The inputs of the Comparators 37-DO are associated with the main outputs unit 15, the input of the comparator 41 is connected to the output terminal of the key 20. The other inputs of the comparators 37-41 receive a U. signal of the sweep voltage generator 4. The outputs of the comparators 37-41 through the OR element 42 are connected to the input of the counting trigger 43, the output voltage of which Pogo is the output signal of the formation unit 6. At the same time, the duration of the output signal C, block 6, as shown in Fig. 2, is equal to the duration of the pulses of the inverter output voltage curve at a given interval.

An increase in the output frequency of the inverter during the adjustment process is accompanied by a sequential decrease in the amplitude of the sweep signal Uy allocated by the amplitude sensor 5. The signal from sensor 5 minus the voltage of source 18, proportional to the minimum inter-switching pause, is constantly compared at the inputs of circuits 29-30 and 33-34

comparison with the output signals of the adders 8-9 and 31-32, which determine the moments of formation of the fronts of the output pulses. In the case of equality of these signals, which is observed when the output frequency increases, in order to avoid disrupting the switching of the output pulses, the command signals from the outputs

circuits 30,34,29 and 33 comparisons cause the keys 27,28,25 and 26 to be disconnected in series, stopping the supply of the corresponding signals to the inputs of the comparators 37-40. With an increase in the output frequency in the output voltage curve of the inverter, a consistent decrease in the number of pulses is observed.

Simultaneously changing signals

0 at the outputs of the 29-30,33,34 comparison circuit leads to the passage of signals to the auxiliary outputs of the block 15 through the AND 36 element (which occurs when U (, a) or

5 element I 35 (observed at Ug c

0

five

14

U

31

and 19).

Marked mode

five

0

five

Moms work corresponds to the formation of output pulses in the central part of the clock intervals.

These commands through the element OR 16 arrive at the control input of the switch 20 and cause it to periodically close, so that the signal of the sensor 5 of the amplitude of the sawtooth voltage periodically arrives at the positive input of the adder 21. To the other inputs of the adder 21, the arrival of t11 signals removed from the main the outputs of the block 15 (from the output terminals of the keys 25-28 of the block 15) and from the output terminals of the key 20. Due to the marked polarity of the inputs of the adder 21, a signal is generated at the output of it over the entire control range, the magnitude of which is proportional to ionic total pulse duration on the half-period of the inverter output voltage. This voltage U2 is supplied to the negative input of the integrator 22, the positive input of which is connected to a constant voltage source 23, the voltage of which is equivalent to the total duration of the output pulses at the half-period of the output curve at the initial output frequency of the inverter.

Therefore, the output of integrator 22 is zero at the initial output frequency. By increasing

915

the output frequency of the inverter, the zero signal at the output of the integrator 22 remains until the signal disappears from the first of the main outputs of block 15 and, accordingly, the first key closure 7). The resulting signal at the output of the adder 21 after this point in time becomes less than the voltage of source 23, the integrated positive differential signal is fed from the output of block 22 to the positive inputs of adder 8 and amplifier 10, causing a corresponding increase in the duration of the nine output pulses This adjustment sub-band is characterized by the formation of output pulses in the centers of clock intervals of 60-degree durations, the duration of which is reduced. with increasing frequency, in connection with which a positive signal from the output of the integrator 22 will increase the frequency at successively increasing pulse duration remaining output curve. Maintaining a constant total duration

output pulses in a half-wave, the amplitude of the signal U10 of a non-comparable output voltage when the frequency changes and at constant pulse amplitudes corresponds to the law of linear variation of the half-time average value of the output voltage of the inverter1, most often realized in frequency-controlled electric drive systems. The fundamental harmonic of the output voltage varies in this case also according to a law close to linear. The presence of the integrator 22 in the feedback circuit ensures the static character of the adjustment process, thereby increasing its accuracy.

The absolute value of the position of the fronts of the output pulses, specified by the signals of the adders And and 12, in relation to the beginning of the clock intervals in the control process remains unchanged, the change in the duration of the output pulses occurs due to the displacement of other fronts generated by the signals of the adder 8 and the amplifier 10. This the circuit property allows to significantly reduce the number of additional commutation of the power switches of the inverter in the high frequency range close to

0

700

five

0

five

ten

to the nominal output frequency in comparison with the switching quantity of the control algorithm implemented by a known device, in which the regulation of the output voltage is proportional to the displacement of both fronts of the output pulses up to the upper output frequency.

4 shows timing diagrams showing the operation of the converter control system in the region of increased output frequencies when U5 "U. There are no signals at all the main auxiliary outputs of block 15, the half-wave of the output voltage, as shown in Fig. 4a, is formed from three pulses, the fronts of which are set by the constant signal U10 from the output of the amplifier 10. The difference integral signal of the feedback correction circuit from the output of the block

22 on this control band is zero.

The described algorithm of the circuit operation is preserved until, in the process of further increasing the frequency

five

0

five

0

five

c with the voltage U at the output of the adder 19, after which the signal from the output of the comparison circuit 24 opens the switch 20. The specified time (Fig. 46) corresponds to the nominal value of the output frequency of the converter, the output voltage is at the same time maximum and with further increase the frequency remains at that level. The signals at the output of block 6 in this mode are absent, only the clock inputs of the distributor 3 receive signals from the outputs of register 2.

The three-digit control system register 2, which functions as a scaling circuit, divides the pulse frequency from the clock 1 generator and distributes the signals over time (phase shift of the signals). In the digital form, the state of the outputs Qg Q Qf of register 2, starting with the highest bit, for the period of the output voltage can be successively written as 100, 00, 000, 101, 110, 111 (signal U in Fig. 2).

The logic distributor 3 control pulses forms a three-phase system of pulses corresponding to the required order of switching the gates of the inverter power circuit. Distributor 3, which performs 180-degree key management of a three-phase bridge inverter with phases A, B, C with additional switches in the middle 60-degree sections (clock intervals), at which the shape of the output voltage curve over the entire control range depends from the parameters of the load, is a logic circuit, in which logic is applied to the input signals followed by logical summation. Logic functions implemented by the distributor 3 and coming in the form of The controls for the corresponding valves are as follows.

-A "Q4Q3 + Q4U6 + Q2U6; + Q, Q3 + Q, QU + Q, Q6 -f + Q “QaQ U6; + C QjQj + §, UC + Q2U6.

The control pulses to the other vents of the respective inverter phases (+ A, -B, -C) are obtained by logical inverting the corresponding phase signals at the output of the distribution signal. The shape of the inverter output voltage curve with this control algorithm does not depend on the loading parameters, the average switching frequency gates close to constant value.

Thus, due to the fact that the regulation of the voltage of the inverter is carried out by changing the temporary position of one of the edges of the output pulses at the same position of the other front, and also by excluding the connection of the logical node containing the key 17 and the element OR 16, With the input of the formation unit 6 of the pulse durations j, a noticeable decrease in the number of switching power inverter gates is achieved, with a corresponding decrease in the magnitude of switching losses. Particularly, the indicated loss reduction is noticeable in the range of increased output frequencies, in the region of close to the nominal loads of the variable-frequency drive system, in which the converter devices

0

five

0

five

about

five

45

work, as a rule, the longest. For the embodiment of the control system structure shown in Fig. 1, the marked range begins with the equality of signals.

U5 and U ,, U, 5 - UT

 0.4U6m - 0.04U5rn 0.36U5m. i

This corresponds to the fact that, with n 2, for about the upper third of the whole inverter control range, the number of valve commutations of each phase in a half period decreases from 10 (with the device control algorithm) to 6 (with the algorithm of the proposed device) with a corresponding almost twofold decrease switching losses in the converter system.

Claims (1)

Invention Formula A device for controlling a three-phase adjustable inverter containing a source of reference voltage, n main and auxiliary sources of direct voltage, a clock pulse generator connected to a three-digit register connected to the outputs of the clock inputs of the distributor of control pulses, and a sawtooth generator connected to the amplitude sensor of the sawtooth voltage and with the main input of the (2p + 2) -input pulse shaping unit, the output of which is connected to the main input One of the control pulse distributors, (2p + 2) adders, the positive input of the first of which is connected to the output of the sawtooth amplitude sensor, and the negative input with an auxiliary source of constant voltage, the first positive inputs of the even adders and the negative inputs of the other odd ones adders are connected to the output of a voltage source, the second plus inputs of all adders, except the first one, are connected in pairs with the main sources of constant voltage, the outputs of the adders and the source output second voltage connected to the corresponding primary inputs (2n + 2) vhodo- Vågå switching unit provide stability, consisting of two node groups of comparison by n nodes in each, from n adders, n elements And and 2n controlled keys, the main inputs of the specified block through the corresponding controlled keys are connected to the inputs of the shaping unit of pulse durations, the even main inputs of the specified block are associated with the first inputs of the first group of comparison nodes, odd inputs are connected to the first inputs of adders, the second inputs of which are connected to the auxiliary voltage source, and the outputs of which are connected to the first inputs of the comparison nodes of the second group , the second inputs of all comparison nodes are connected to the output of the first main adder, the forward outputs of the comparison nodes of the first group are connected to the control circuits of the even keys of the switching stability unit, the inverse outputs of these nodes are connected to the first inputs of the corresponding And elements, the forward outputs of the nodes Comparisons of the second group are connected to the second inputs of the corresponding elements Nick to the control circuits of odd keys, the outputs of the AND elements through the OR element are connected to the control circuit of the main key, which is That is, in order to reduce the switching losses in the inverter during the associated frequency control and the output voltage, it is equipped with an integrator with two summing inputs% 0 five 0 five 0 five , a multi-input adder, a comparison unit, an additional control key, an additional DC voltage source and a summing DC amplifier, the first input of the summing DC amplifier being connected to the output of the voltage source, the summing amplifier output is connected to the first input the comparator unit, and through an additional key with the (2n + 2) th input of the pulse duration unit, the second input of the comparator unit is connected to the output of the first main adder, the output of the unit It is connected to the control circuit of the additional key, the amplitude output of the sawtooth voltage is connected to the input terminal of the main key, the output terminals of both keys and the odd main outputs of the switching stability unit are connected to the positive inputs of the additional totalizer, the even basic outputs of the switching stability module are connected to the minus inputs of the additional adder, the output of this adder is connected to the minus input of the integrator, the plus input of which is connected to an additional source of DC voltage, and the integrator output is connected to the second input of the summing amplifier and to the third plus inputs of all even main adders, except the last. FIG. g m „ / V NUTYUT About Q 4