SU1527637A1 - Device for checking computer programs - Google Patents

Abstract

The invention relates to computing and can be used in software debugging devices, industry monitoring devices for the execution of digital computer programs. The purpose of the invention is to increase the diagnostic capabilities of the device by controlling complex operators that compute elementary monotonically increasing functions within the interval of reference values. The device contains registers 3, 4, 9, comparison circuits 5, 6, drivers 7, 8 pulses, trigger 10, AND 11 element, delay element 12, OR 13 element, AND 14 element, interval selection block 15 with corresponding connections. 1 hp f-ly, 2 ill.

Description

Zi

(L

w

figure 1

The invention relates to computing technology and can be used in program debugging devices, devices for controlling the compliance of programs of digital computers,

The purpose of the invention is to increase the diagnostic capabilities of the device due to the control of complex operators that compute elementary monotonically increasing functions within the interval of reference values.

Fig, 1 shows a diagram of the proposed device; FIG. 2 is a block allocation circuit diagram;

The device contains address, first 2 and second 7. „information inputs, registers 3 and 4, first 3 and second 6 cxeMi i comparison, first 7 and second 8 pulse shapers, register 9, trigger 10, element 11, delay element 12, element OR 13, element AND 14, interval selection block 15, 16 function errors, output 17 error arguments,

The interval allocation block 15 contains the argument register 18, the register group 19 reference argument values, the first 20 and second 21 groups of AND blocks, the trigger 22, the group of comparison circuits 23, the AND group of elements 24, the OR 25 element, the register group 26 of the normal function , the third 27, the fourth 28 and 29 groups of blocks of elements AND, the first-vno 30 and the second 31 groups of elements OR, the register

32inzhner Granina interval, register

33 top Granina interval, first

34 and the second 35 comparison schemes. The device works as follows:

all at once

In the initial state, register 3 records the value of the code of the command counter of the digital computer in which the controlled operation is performed, in register 4 the value of the code of the command counter of the digital computer in which the argument for the controlled function is calculated, in registers 19, -19, the reference values of the arguments the reference values of the function argument, in registers 20, - 20 "values of functions, are the corresponding calculated values of the function. The remaining registers and triggers of the device are reset.

The value of the address of the command counter of the digital computer is fed to input 1 to circuits 5 and 6 of the comparison. If this value coincides with the code registered in

In line 4, a pulse appears at the output of the comparison circuit, KOTOpbtfi is fed to the input of the delay element 8 and the clock input of the interrupt allocation unit 15 is present. On the information input of the interval allocation block 15, the value of the argument of the function (X), which arrives at the remote control 2.2, is written to the argument register 18. The contents of register 18 of the argument and registers 1P - 1H (reference values of the argument through the corresponding groups (first and second) of the blocks of elements And 20 and 21, open, and upon receipt of the sync pulse at the input of the trigger 22, which translates it into a single state, to the corresponding circuits 23, - 23 comparisons. In case the argument value falls outside the bounds of the permissible interval of change, a single signal appears at the corresponding outputs of the circuits 23 and 23, which, passing through the OR 25 element, arrives at the output 17 of the argument error, AT rotivnom case of a single signal is outputted from the i-th Equals circuit 23; comparison (i 1, n), if the contents of register 18 match the contents of the argument i-ro register 19) the reference values of the argument, t, e,

  .Ti.

or at the outputs. More than those comparison circuits 23, the contents of the corresponding registers 19 reference values of the argument which are greater than the contents of the register 18 of the argument, t, e,

,,

and at the outputs less than the rest of the comparison circuits 23. A single signal appears at the output of that element of group 24, (l-ktN-l), whose inputs are connected to circuits 23);

and 23

comparing with the corresponding

registers °. and 19 + 1 stage values of arguments, the contents of which are respectively smaller and larger than the contents of register 18 of argument,

those.

, X ,,, x or x ..

K + 1

In the first case, a single signal from the output is equal to the i-th circuit 23; comparison opens the corresponding block of elements AND 2Pj of the fifth group and allows the transfer of the contents of the register to the function 26; through the nerve and second group of elements OR 30 and Jl

n registers 32 and 33 of the nerves and lower limits of the interval, and further to the notes of the corresponding schemes 3 and 35 of the comparison.

In the second case, a single signal from the output of the k-ro unit of the group IL element opens the corresponding blocks of elements 27 and 28, the third and fourth groups and allows the transfer of the contents of the 2fS register of the function value through the first group of elements OR 30 to the register 32 of the lower interval width, and the contents of register 26, the value of the function through the second group of elements OR 31 into the register 33 of the upper limit of the interval, and then to the inputs of the corresponding circuits 34 and 35 of the comparison.

The impulse delayed in element 8 arrives at the single input of the trigger 10 and sets it to the single state. With the trigger 10 high potential arrives at the first input of the element And I 1,

When the code value of the instruction counter address matches the value recorded in register 3, which means the instant of the start of execution in the program of the controlled operation, the signal appears at the output of the comparison circuit 5. This signal is delayed and generated by the shaper 7 at the time of the monitored operation, fed to the second input of element II, as well as to the control input of register 9, opening it and allowing the value of the received function f (x) to be written from the first information input 2 of the device to the register 9, If at the inputs of element 11 are single signals, which corresponds to the event of presence in register 9 of the value of the function f (x) and the presence of interval values in registers 32 and 33, then the output of element II II is a pulse arriving at the input of element 12 zader , the zeroing input of the triggers 10 and 22, as well as the control inputs of the comparison circuits 34 and 35,

In comparison circuit 34, an operation is performed to compare the obtained value of the function f (y) with the value of the lower limit of the interval. If the value of the function f (x) 1- {is smaller than the value of the lower limit of the internal, then the output of the comparison circuit 34 is a signal arriving at the input of the element OR 13, In the comparison circuit 35, an operation is performed

0

five

0

comparing the resulting value of the function f (x) with the value of the upper grlic interval. If f (X) is greater than the value of the upper limit of the interval, then at the output of the comparison circuit 35, a signal appears (input to the element of the IPD 13, the impulse delayed in the element 12 for the duration of the comparison operation is fed to the input of the element 14, If a signal is present at the output of one of the comparison circuits 34 and 35, then it, passing through the elements 111-113 and 14, goes to the output of the error of the function Ifi,

Claims (1)

Invention Formula I. A device for the counting program count control, containing the first and second comparison circuits, two shapers and a shulsor, a register, a delay element, two AND elements, an OR element, and the address input of the device is connected to the first input of the first comparison circuit, 5 increasing the diagnostic capabilities of the device by controlling complex operators that compute elementary monotonically increasing functions within the interval of reference values; the second and third registers, the trigger and the block of int The device’s input is connected to the first input of the second comparison circuit, the equality output of which is connected to the sync input of the slot block, the outputs of the first and second registers are connected respectively to the second inputs of the first and second comparison circuits, the equality outputs of which are respectively through the first and second pulse shapers are connected to the input of the third register and with a single trigger input, the output of the first form of the pulse generator is connected to the first input of the first element, And the output of the first element This AND is connected to the zero input of the trigger, to the polling input of the interval selection block, through the delay element to the first input of the second element AND, the inputs of the value of the monitored function are connected to the information inputs of the third register, the output of which is connected to the first information input of the allocation block; the trigger is connected to the second input of the first element AND, the input argument of the device 0 five 0 five 0 five connected to the second one with the input input of the isolation block, the second and second error outputs of the monitored function and the error output of the interval allocation argument unit are connected respectively to the first and BTOpi.iM inputs of the OR element and the error output of the device argument element And, the output of which is the output of the bending of the monitored function of the device. I 2, The device according to claim 1, characterized in that the block allocation interval contains n registers of reference argument values (where n is the number of control 1, gu: intervals), the argument register, the first, second, third, fourth, fifth and sixth groups of elements And, trigger, n comparison circuits, OR element, n function value registers, first and second groups of OR elements, upper and lower interval boundaries registers, first (n + 1) -th and (n + 2) -th comparison schemes, input the argument value of the block is connected to the information input of the register of the argument, the input is synchronized This unit is connected to a single trigger input and an input to the register of the argument, the information output of which is connected to the cervical inputs of the elements And the first group of outputs from the registers of the reference values are connected to the first inputs of the elements of the second group, the direct output of the trigger And the first and the second group, B1-1x of the elements of the 1st group (where i 1, n are connected respectively with the first and second inputs of the i-th circuit (, 1 comparison, the output MeHT.i ie the first 0 five 0 five 0 The groups and Volta of the nth comparison circuit are connected, respectively, with the first and second inputs of the OR element, the 5th output of which is the error of the args of the unit, the output is Less than the ith comparison circuit, with the first thermal input (: - 1) of the And the third group, the output of the More i-th comparison circuit is connected to the second inputs of the iro element of the third group, the outputs of the register of reference values (Functions connected to the first groups of elements of the fourth, fifth and sixth -cfi groups, output of the i-ro element The third group is connected respectively to the second inputs of the i-ro element That of the fourth and fifth groups, the equality output of the i-th circuit, the comparison is connected to the second stroke of the 1st element and the sixth group, the output of the i-element of the element And the fourth group is connected to the i-th input of the elements OR of the first group, the output of i- ro element And the fifth group is connected to the i-th input of the OR elements of the second group, the output of the i-ro element of the sixth group is connected to the (n + i) -M input of the OR elements of the second and third groups, the outputs of the OR elements are connected to the information inputs of the registers the upper and lower limits of the interval, the outputs of which are connected to the first inputs of the corresponding the (n + 1) -th and in + 2) -and comparison circuits, the polling input of the block is connected to the zero input of the trigger and the clock input of the (n + l) -th and (n + 2) -th comparison circuits, in or- The on-line input of the unit is connected to the second inputs of the (n - 1) -th and (n + 2) -th comparison circuits, the outputs of the More (n + 1) -th comparison circuit 1-1 and Less (n + 2) -th comparison circuit are the first and second block error outputs respectively. it. t If