SU1524035A1 - Digital oscillator - Google Patents

Abstract

The invention relates to a measurement technique and can be used to generate various periodic signals. The purpose of the invention is the expansion of the class of tasks due to the possibility of forming functions with a truncated period. The digital generator contains 1 clock pulse generator, 2 frequency divider, address counter 3, memory block 4, digital-to-analog converter 5, DC amplifier 6, first 7 and second 9 registers, element 8, code comparison device 10 and button switch 11 The generator generates periodic signals of various forms with both a full period and truncation. The goal is achieved by the introduction of registers 7, 9, element 8, comparison device 10, and a push-button switch 11. 2 sludge.

Description

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The invention relates to a measurement technique and can be used to generate signals representing periodic functions of time of various shapes.

The purpose of the invention is the expansion of the class of tasks due to the possibility of forming functions with a truncated period.

FIG. 1 shows a functional diagram of a digital generator; in fig. 2 - time diagrams that show his work.

The digital generator contains 1 clock pulse generator, 2 frequency divider, address counter 3, amplitude memory block 4, analog to analog converter 5, direct current amplifier 6, first register 7, element 8 and 8 second register 9, device 0 code comparison, button switch one

The amplitude memory (ROM) contains instantaneous values of the period of the signal of the required shape with a uniform time discretization and the number of split points of the period n.

Before starting work, the division factor is set to divide frequency 2, the first register 7 records the code of the number k, the number k - the start point of the period when the signal is placed, the second register 9 records the code of the number ta, the number m - the end point of the period when forming signal.

The digital generator works as follows.

From the push button switch 1 1, through the second input of the element 8, the input of the information record of the address 3 is sent to the signal, by which the code of the number k is written to the counter 3 of the address. Upon receipt of clock pulses from the generator output through a divider 2 frequency to the counting input of the counter 3 addresses, the counter 3 addresses start counting from the number k, the signals from the output of the counter 3 addresses go to the address inputs of the block A and through the PAP 5 and the DC amplifier 6 to the generator output generates an analog signal recorded in block 4, but its period does not start from zero, but from the k-ro count, while the signals from the output of counter 3 of the address go to the second inputs of device 1

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code comparison, the first inputs of which through the second register 9 set the number t. When the output of the counter 3 address is set to a code equal to the number t, the signal comparison device 10 will receive a signal through the first input of the And 8 element and the input of the information record of the counter 3 address will receive a signal but to which the number k will be set again at the output of the address 3, and the formation of the second period will begin, the further operation of the digital generator is repeated.

If k O and m p, then a signal with a HOJHibiM period of a given frequency will be generated at the generator output. For generating signals with a truncated period, the numbers k and m can have iipHHVMaTb values n, and k.

Claims (1)

Invention formula 1 + and A digital generator containing a clock pulse generator, a frequency divider, an amplitude memory block, an address counter, and a generator period input input is connected to a control input of a frequency divider whose output is connected to the counting input of an address counter, a clock pulse output is connected to the entrance de. iggel frequencies, which are distinguished by the fact that, in order to expand the class of problems to be solved, due to the possibility of forming functions with a truncation-1 period, two registers were entered into it, a code comparison device, a push-button switch, and an element, the output of the first register write the address counter, the write enable input of which is connected to the output of the element I, the first input of which is connected to the zero signal level through a second switch, the second input of the element AND is connected to the output of the comparison device codes, the nerve informational input of which and the input of the memory block. The amplitudes are connected to the output of the address counter, the second information input 5 input of the device is mismatched (hells are connected to the output of the second register, the output of the amplitude memory is connected to the generator. and , / G-5U, t 191