SU1520654A1 - Device for checking pulse sequence - Google Patents

Abstract

The invention relates to a pulse technique and can be used in instrumentation and automation devices. The purpose of the invention — extending the functionality — is achieved by providing control at different mutual temporal positions of the input pulses regardless of their duty cycle. For this purpose, a trigger 4, two elements AND 5 and 8, two elements OR 13 and 16, a delay element 18, a back edge pulse generator 12 and the corresponding functional connections are introduced into the device. In addition, the device contains triggers 1-3, the AND-HE element 9, the AND elements 10 and 11, the delay element 17, the input buses 19 and 20, the output bus 21. The control of two pulse sequences is provided with both time-alternating pulses and with mutually overlapping pulses in part or in time, regardless of their duty cycle. 3 il.

Description

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The invention relates to a pulse technique and can be used in instrumentation and automation devices.

The aim of the invention is to enhance the functionality by providing control at different mutual temporal positions of the input pulses regardless of their duty cycle.

Figure 1 shows the structural diagram of the device; 2 and 3 are timing diagrams explaining the operation of the device.

The device contains the triggers 1 - elements And 5-8, element And-NB 9, elements And 10 and 11, the driver 12 of the rear front. Pulses, elements. OR 13-16, elements J7 and 18 delay, input 19 and 20 and output 21 tires . The input bus 19 and 20 are connected respectively to the first inputs of the elements 6 and 7, to the clock inputs of the triggers; I and 2, to the combined first inputs and to the combined second inputs of the AND 5 and OR 14 elements. The output of the OR element 14 is connected to the input of the back edge of the pulse former 12, the output of which is connected to the clock inputs of the triggers 3.4 and 8,10, the second inputs of which are connected to the output of the element-AND-NOT 9, and the third inputs, to the inverse output of the trigger 4. The output of the element And 5 is connected to the input of the installation in the unit of the trigger 3, the inverse output of which is connected to the first inputs of the elements And -NO 9 and 11, and the direct output is at the installation input to zero l trigger 4 and with the first inputs of the elements of 1 SHI 15 and 16, the second inputs of which are connected respectively to the third and second inputs of the element AND-HE 9 and the outputs of the ele. cops 18 and 17 delays. The inputs-elements 17 and 18 of the delay are connected respectively to the inverse outputs of the flip-flops 1 and 2, the installation inputs to zero of which are connected respectively to the outputs of the And 8 and 10 elements, the fourth inputs of which are connected respectively to the outputs of the IIR elements 15 and 16. The direct outputs of the triggers 1 and 2 are connected respectively to the second inputs of the elements 6 and 7, the outputs of which are connected respectively to the first and second inputs of the element 1-XI 13, the output of which is connected to the output bus 21

and with the second, the input element and 11, you.

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20 25 ZO f. 5 CQ -

the course of which is connected to the input of the unit in the trigger unit 4.

The device works as follows.

In the initial state, the triggers 1-4 are in the zero state (the reset circuits of the triggers are not shown). Element And 5 is closed on both inputs with zero signals on input buses 19 and 20, elements 6 and 7 are closed on first inputs with zero signals from input buses 19 and 20 respectively, and on second inputs with zero signals from direct outputs of triggers 1 and 2, respectively. Elements 8 and 10 are closed on the first inputs by a zero signal from the output of the driver 12 pulses, element I-HE 9 is open on all: the inputs with single signals from the inverse output of Trigger 3 and from the outputs of the delay elements 17 and 18, respectively. Elements 8 and 10 are also closed on the second inputs by a zero signal from the output of the element AND-HEN 9 and open on the third inputs by a single signal from the inverse output of trigger 4 and on the fourth inputs by single signals from the inverse outputs of trigger 2 and 1, respectively, coming through element 18 delays, the SHSh 15 element and the delay element 17, the OR element 16, respectively. Element 11 is open on the first input with a single signal from the inverse output of the trigger 3 and. is closed at the second input by a zero signal from the output of the element OR 13.

Let us consider the operation of the device for the case of alternately incoming pulses of sequences P and F (from input buses 9, 20) without overlapping time pulses. Chart of work. The devices for this case are shown in FIG. 2, where the numbering of the potential diagrams corresponds to the numbering of the circuit elements in FIG. 1.

The first pulse, for example, the sequence Ff comes from the bus 19 to the clock input of the trigger 1, to the first input of the element AND 6 and through the element OR 14 to the input of the driver. 12 pulses. On the trailing edge of the pulse F, the trigger 1 is switched to the single state, the element AND 6 remains closed, at the output of the driver 12 a pulse is generated that arrives at the clock inputs of the trigger i 3 and 4 and confirms their initial one;

zero state. The pulse from the output of the imaging unit 12 is also fed to the first inputs of the AND elements 8 and 10, which remain closed at the second inputs by a zero signal from the output of the AND-HE element 9, since after switching to trigger one state at the output of the delay element 17

bus 21, will generate a signal failure. The pulse from the output of the element OR 13 also opens the element AND I1. With the pulse at the output of the element And 11, the trigger 4 is switched to one state and closes with the zero signal of the inverse output through the third inputs the elements And 8 and 10. At the end

and, accordingly, at the second input of the Q pulse Fj, a pulse is generated at

ment-AND-NOT 9 over time

but

the output of the driver 12, which arrives at the first inputs of the elements of And 8 and 10, closed at the third inputs, and at the clock inputs of the triggers 3 and 4

but

single signal is saved. After the time C a, a single signal appears at the output of the NAND 9 element.

Pulse duration Ots form-15 At the end of the pulse of the driver 12, the output state of the driver 12 is slightly longer than 12, the zero state of the trigger 3, which is required for reliable switching, is confirmed and the trigger 4 switches to the zero state, and then at its inverse output only a large signal f c of the formation-20 again appears a single signal, the tel 12. arriving at the third inputs of the elements At the end (at the falling front) of combs And 8 and 10.

the trigger, the delay time from the delayed delay elements 17 and 18 is selected to the unavailable from the pulse bus 20, the trigger 2 switches to one state, the And 7 element remains closed, and a pulse is again generated at the output of the driver 12, which confirms the initial state of the trigger 3 and 4 , opens the element AND 8, since at its fourth input for a time, „0 after the switching of trigger 2 is retained

30) F pulses, (F - Failure to the output bus 21 is received during the whole time of the loss of F pulses, (F, i). After restoring the sequence F (F), the device is repaired, it increases the Failure signal.

Thus, when a pulse is lost in one of the monitored sequences, the F (F) signal

Failure occurs on the output bus

a single signal through the element OR I5 from the output of the element I8 delay. The impulse from the output of the element And 8 switches the trigger 1 to the initial state.

With the arrival of subsequent time-alternating pulses F,, F, the device operates similarly to Q 21 with the arrival of the next (first first after the second) pulse of another after the end of each pulse ().

F4 (F, 2) switches to a single connection. Consider the operation of a device for trigger 1 (2) and return in the case of overlapping in time the initial state of a pulse from the output of pulse sequences F and F r./rr meander.

With the arrival of the pulse F, (according to the diagram of FIG. 3, the operator is shown) the element OR 14 is opened, the output of which is fed to the input of the driver 12; With the arrival of the pulse F, then the element 5 opens, the output signal of which switches the trigger 3 to one state, after which the zero signal from its inverse succession F opens the output element 7/2 output to the first input since the trigger 2 is in the unity element -NOT 9, a single signal with the nominal state and passes from its output, which opens on the second turn through the element ШШ 13 to the output inputs of the elements 8 and 10. On the exponent 12, trigger 2 (1). At the same time, elements 6 and 7 remain closed and a signal of failure at the output of the element OR 13 and, accordingly, is not formed on the output bus 21.

If, after passing the next pulse, for example, the FM sequence does not form (is missing) the pulse of the sequence F (Fig. 2, dashed line), then the next pulse after 50

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the output of the driver 12, which arrives at the first inputs of the elements And 8 and 10, closed by the third inputs, and to the clock inputs of the triggers 3 and 4.

The device operates in the same way in the case of a missing pulse of the 25th sequence of the F .. Only in this case, the signal fails to the output bus 21 through the element OR 13 from the output of the element 6. And if several pulses disappear

30) F pulses, (F - Failure to the output bus 21 is received during the whole time of the loss of F pulses, (F, i). After restoring the sequence F (F), the device is repaired, it increases the Failure signal.

Thus, when a pulse is lost in one of the monitored sequences, the F (F) signal

Failure occurs on the output bus

Q 21 with the arrival of the next (the first after the failure) pulse of another 50

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chapin pulse F switches to

single state. trigger 1. By

the end of the pulse F- switches

in a single state, trigger 2, F pulse, switches to a single

Thus, the duration of the Failure signal is equal to the duration of the input pulse F (F). At the end, the element OR 14 is interrupted and a pulse is formed at the output of the imaging device 12, which opens the elements AND 8 and 10, the output signals of which switch to the zero state, respectively, triggers 1 and 2. On the falling edge of the impulse from the imaging device. 12 switches to the zero state of trigger 3 and confirms the zero state of trigger 4. After switching to zero state of trigger 1 after a time (5p, a single signal appears at the output of the delay element 17 and goes to the second input of the AND – HE 9 element The output of which is a zero signal.

When a queue of the first pulse F is received and the corresponding pulse F is absent (lost) (FIG. 3, dashed line), the device works as follows.

At the end of the pulse, F switches to a single companion trigger.

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the state of the trigger 2, and at the output of the imaging unit 12 a pulse is generated, which passes through the elements 8 and 10 and returns the triggers 1 and 2 to the initial zero state. On the trailing edge of the pulse of the former 12, the trigger 3 returns to the zero state. After the triggers 1 and 2 are switched to the zero state, on the outputs of the J5 elements 17 and 18 of the delay, single signals appear at the output of the delayed Cjoioi, and 9 is a zero signal and the circuit returns to its original state.

Thus, the design features of the proposed device allow to expand the control possibilities as compared with the known device, in which, when controlling sequences, in which the pulses F and F completely coincide in time and are in the form of a meander, the duration of the error decreases to a vanishingly small value

20

25

1, with the output of the element 17 being closed (in the order of the response time of one or three logic elements of the circuit).

holding for the time 6. „a single signal is saved, and at the output of the AND-BAY 9 element a zero signal. Therefore, the pulse from the output of the driver 12 does not pass to the output of the element AND 8 and the trigger 1 remains in a single state. The appearance through time o qq. the output of the element 17 of the delay of the zero signal. on the output of the element AND-NOT 9 there is a single signal.

With the next pulse F then arrives, the latter passes through the AND 6 and I-fflH 13 elements to the output bus 21, forming the Failure signal, and simultaneously opens the AND 11 element, at the first input of which there is a single signal from the inverse output of the trigger 3. Pulse from the output element 11 switches to one state trigger 4. With the arrival of pulse F then (before the end of pulse F), element 5 opens and switches to one state trigger 3, switching the single signal to the zero output 4 to the zero state. imp F lsa stopped formation failure signal on bus 21.

pulse F switches to single

Thus, the duration of the signal failure is equal to the duration of the input pulse F (F). At the end of them

the state of the trigger 2, and at the output of the imaging unit 12 a pulse is generated, which passes through the elements 8 and 10 and returns the triggers 1 and 2 to the initial zero state. On the falling edge of the pulse of the former 12, the trigger 3 returns to the zero state. After the triggers 1 and 2 are switched to the zero state, single outputs appear at the outputs of the delay elements 17 and 18, and at the output of the NAND 9 element - a zero signal and the circuit returns to the initial state.

Thus, the design features of the proposed device allow to expand the control possibilities as compared with the known device, in which, when controlling sequences, in which the pulses F and F completely coincide in time and are in the form of a meander, the duration of the error decreases to a vanishingly small value

(on the order of the response time of one or three logic elements of the circuit).

In the proposed device, the control of two impulse sequences is provided both with alternating impulses (alternating) in time pulses, and with mutually overlapping (partially or completely) pulses in time regardless of the duty cycle.

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Claims (1)

Claims An apparatus for controlling a sequence of pulses, comprising first, second and third triggers, first, second, third and quarter AND elements, AND-NOT element, first and second SHSh elements, first delay element, two input buses, the first of which are connected with the first inputs 11 of the first and second elements I and with the clock input of the first trigger, the direct output of which is connected by the second input of the second element AND whose output is connected to the first input of the first OR element, the second input of which is connected to the output of the third The terminal And, the entrance to The second input is connected to the clock input of the second trigger, and the second input to its direct output, the output of the first element I is connected to the first input of the third trigger, the inverse output of which is connected to the first input of the NAND element, the second input of which is connected to the output of the first delay element , the output of the first element OR is connected to the output bus, characterized in that, in order to expand the functionality by providing a control, the role at different mutual temporary position of the input pulses regardless of their duty cycle the fourth trigger, the fifth and sixth elements are AND, the third and fourth elements OR, the second delay element and the pulse shaper, whose output is connected to the clock inputs of the third and fourth triggers and the first inputs of the fourth and fifth elements AND the second and third inputs of which are connected respectively, with the element of the NAND element and with the inverse output of the fourth trigger, the fourth inputs of the fourth and fifth elements of the AND connected % Y / 0 five five 0 respectively, with the outputs of the third and fourth elements OR, the first inputs of which are connected to the direct one, the output of the third trigger, and the second inputs are connected respectively via the second and first delay elements with the inverse output of the second and first triggers, the installation inputs in O which are connected respectively to the output of the fifth and fourth elements AND, the input of the pulse former is connected to the output of the second OR element, one input of which is connected to the first input bus and the second input to the second input bus, to the second input of the first about the AND element and the clock input of the second trigger; the inverse output of the third three-timer is connected to the first input of the sixth element AND, the second input of which is connected to the output of the first element OR, the sixth element AND is connected to the input of the unit of the fourth trigger, the installation input in О which is connected to the direct output of the third trigger, the third input of the NAND element is connected to the output of the second delay element. F & 2 0if9.5