SU1518680A1 - Counter of photons - Google Patents

Abstract

The invention relates to the field of measurement and can be used to register weak and super-weak light fluxes in the physics of laser atmospheric sounding, space research, chemistry, and astronomy. The goal is to improve measurement accuracy by increasing the rate of accumulation of information. The device contains series-connected PMTs, a discriminator of single-electron pulses, a block of N triggers, as well as a block of RAM, a computer, a timing circuit, a mode trigger, a controlled clock generator, a ring shift register, a clock frequency divider by N, an address word counter, and the output of the PMT connected to the input of the discriminator of single-electron pulses, its output is connected to the first inputs of photon triggers, the output of RAM data is connected to the input computer register, the output of the synchronization circuit is connected to the first input of the mode trigger, its the output is connected to the input of the controlled clock generator, and to the first control input of the RAM, the output of the controlled clock generator is connected to the inputs of the ring shift register and the clock divider to N, the outputs of the ring shift register are connected to the second inputs of the photon triggers, the output of the divider by N is connected to the input of the address word counter, its control output is connected to the mode trigger input, as well as the temporary data storage register, the OR gate, the reversible counter, and additional RAM, with the outputs photon gages are connected to the N-bit temporary storage register, the outputs of the temporary storage register are connected to the first control inputs of the RAM and to the N inputs of the OR gate, the output of the OR gate is connected to the "Counting" input of the reversible counter, to the second control input the first RAM and the control input of the second RAM; the outputs of the reversible counter are connected to the address inputs of the first and additional RAM; the control output of the reversible counter is connected to the second computer register, the output register EV connected to the input "Account back" down counter mode latch output is connected to the second input of the additional control RAM address outputs of the address counter are connected to data inputs of additional RAM, its data outputs connected to an input register of a computer. 1 il.

Description

The invention relates to measurements and can be used to register weak and super-weak light fluxes in space research, chemistry, astronomy, etc.

The purpose of the invention is to improve accuracy by increasing the rate of accumulation of information.

The drawing shows the functional diagram of the device.

The device contains a photomultiplier tube (PMT) 1, a discriminator 2 single-electron pulses, a circular shift register 3, a photon trigger block 4, an N-bit temporary data storage register 5, a logical element OR 6, the first electronic storage device (RAM) 7, reversible counter 8, computer 9, synchronization circuit 10, mode trigger 11, controlled clock generator 12, clock frequency divider 13 to N, address counter 14, second 1 5.

The output of the PMT 1 is connected to the input of the discriminator 2 single-electron pulses, its output is connected to the first inputs of the block 4 of photon triggers. The photon trigger outputs are connected to the N-bit register 5 temporary storage data, its outputs are connected to the OR logic input and to the first control inputs of the first RAM 7. The information output of the first RAM 7 is connected to the first input of the mode trigger 11, its output - to the input of the controlled clock generator 12, to the second control input of the second RAM 15 and to the third input of the first RAM control 7. The output of the controlled clock generator is connected to the input of the ring shift register and to the input of the clock divider 13 s on N. The outputs of the ring shift register are connected to the second inputs of block 4 of photon triggers. The output of the clock divider 13 to N is connected to the input of the address counter 14 ,; the outputs of which are connected to the information input of the second RAM 15. The information output of the second RAM 15 is connected to the input register of the computer 9. The control output of the address counter 14 is connected to the second input of the mode trigger 11. The output of the logic element OR 6 is connected to the input of the Forward counter of the reversing counter 8, to the second control input of the first

ten

15

20

25

thirty

35

40

45

50

55

RAM 7 and to the first control input of the second RAM 15. The information output of the reversible counter 8 is connected to the address inputs of the first 7 and second 15 RAM. The control output of the reversing counter 8 is connected to the input register of the computer 9. The output register of the computer is connected to the input The count back of the reversing counter 8.

The device works as follows.

Controlled 1 generator 12 is triggered by a signal from the output of mode trigger 11, which is controlled by a pulse from synchronization circuit 10. This pulse determines the beginning of the registration cycle for input single-electron pulses. With the trigger 11 of the mode, the first 7 and second 15 RAMs are set to the Record mode.

The controlled clock generator I2 generates a sequence of pulses for shifting the resolution pulse of recording the input data from discriminator 2 into the block 4 triggers of photons. This sequence is formed by a ring 3 shift register. The moment of arrival of the photopulse is fixed by writing the unit to that photon trigger, in which at this moment of time there are units on both inputs. After the unit is written to the last Nth photon trigger, divider 13 by N produces a control pulse, according to which information from the photon trigger is copied to temporary data storage register 5, and the byte address number is incremented by address counter 14 by one. Then, the next cycle of fixing the moments of arrival of the photo pulses by the passage of a new series N of enabling pulses in the circular shift register 3 begins. At this time, the input to the output of the temporary storage register 5 appears.

If at least one photo pulse arrives during the previous fixing cycle, the pulse through the logical element OR 6 is fed to the input. The count is ahead of the reversing counter 8 and increases by one the address of the cells of the first 7 and second 15 RAM, into which the position of the bit is recorded. (in RAM 7) and the number of the word in which the arrival of a photo pulse was observed (second RAM 15). The same impulse with

515

the output of the logic element Ш1Н 6 records the state of the register 5 of temporary storage of data and RAM 7 and the address of the word, at which the photo pulses from the address counter 14 into the second RAM 15 are recorded.

If in the current registration cycle no single impulse arrives, then the register 5 of the temporary storage of data will contain zeros in all bits. The output of the logical element OR 6 - zero level. The state of the reversible counter 8 does not change. The write enable signal on RAM 7 and 15 is not received.

Thus, information on the arrival times of the photo pulses is recorded in successive cells of RAM 7 and 15 and only when this information is available. In this case, the moment of arrival of the photo pulse is defined as

t AOR ,, d "yd + N ,,,

where is the address status

counter 14 words, recorded in the i-th cell of the second RAM 15; N is the number of bits (bits) in the word recorded in RAM 7 in the i-th cell. After passing through all possible states, the address counter 14 generates a signal for the end of the registration mode, according to which the trigger II of the mode transfers the RAM 7 and 15 to the Read mode and disables the operation of the controlled clock generator 12.

If a number is registered in the reversible counter 8, which determines the number of words in which the arrival of photo pulses was recorded, then a control signal appears at the control output, which is perceived by the computer 9 as a data transfer readiness signal in the computer's RAM 9. At this, EVI reads the addresses of words and a bit, forms an executive address from them and adds a unit to the contents of a computer RAM cell with this address.

Thus, there is an accumulation of information B cells of computer RAM. After the end of the cycle the summation of the computer generates a signal on which the number of the addressable cells of RAM 7 and 15 is reduced by one and after anal

0

The output of the reversing program 8 again repeats the cycle of transmitting and accumulating data 13 of the JBM RAM. Kgli as a result of the analysis makes it clear that it is empty, i.e. all p. 1; ki OZ set1) are read, the psrechr device;: 1 t of the registration per register, which is recorded with the next spphro1 pulse.

Thus, the changing device

there is no procedure a; llyz of the contents of each cell of RAM leads to a significant reduction in n, because of reading information from the RAM ycTpoi icTjsa, and

therefore, it allows to increase the frequency of the following zones / and gu-fmgh No. 1-jiyjibcoiJ, and, in their own ort, gtrachracht HTJ, time accumulated nibor-g-; J: ITUI :: computer memory, The less iipeMH needles atimshch fl 1pchos, -; them

parameters and a but the scope, -.-. K i.-I N: cni.myio the value they change is irm and impacted, therefore, r; tMn np..s-tc accuracy. At the expense of c OK aiii: p, s -: p RAM decreases it and 01lt} -sh and

power consumption, nosr; and: 1, plszh- HocTi. devices; .

Formula n 3 about b with t and N and

Photon counter, co ;; Lp ,, n, iHii .- add up to the included pholes lvl iv i. MMi multiplier and disk opt. O; u j .- irons pulses, and all-round N photon triggers, bls i s; .o u one-- paTHi Horo is a memory device XI, a computer, a synchro scheme, a trigger, a trigger, controlled by a tact; rator, ring shift register, lsigol clock frequency on N and address

counter, the output of the .11111 single-electron pulse controller is connected to the first inputs of photon triggers, the second inputs of which are connected to the outputs of the ring shift register, the output of the synchronization circuit is connected to the first input of the mode trigger, the output of which is connected to the input of the controlled clock generator and to the first control input the first operative memory, the information outputs of which are connected to the input computer register, the output of the controlled clock generator is connected to the inputs of the ring register

55

the shift and clock divider by N, the output of which is connected}) to the input of the address word counter, the control output of which is connected to the second input of the mode trigger, which means that, with rioBbmieiinH accuracy, an N-bit is entered into it the temporary storage register, the logical element OR, the reversible counter and the second random access memory, the outputs of the photon triggers are connected to the N-bit temporary storage register whose outputs are connected to the N first control inputs of the first onepaTJCBHoro record of the repeater and to the N inputs of the logic unit 1SHI, the output of which is connected to the input of the Account forward of the reversible counter, to the second input of the control unit of the operating network of the device, to the first input

control of the second random access memory, the second control input of which is connected to the output of the mode trigger, the output of the control of the reversible counter is connected to the input register of the computer, the output register of the computer is connected to the input Back of the reversible counter, the information outputs of which are connected to the address inputs of the first and second operational memories , the address outputs of the address counter are connected to the information inputs of the second random access memory, the information outputs of which pogo connected to the input register of the computer.

Rector.I.Kasarda

Compiled by E.Makalkin

Tehred L. Serdyukova Proofreader L. Bezkid

Chuckles, 6598/46

Circulation 466

AMIINI State Committee for Invention and Discovery at the State Science and Technology Committee of the USSR 113035, Moscow, Zh-35, 4/5 Raushsk Nab.

Subscription

Claims (1)

Claim Photon counter, content sequentially connected with an optical fiber multiplier and discriminator sdao. '.' South.ron pulses, as well as a block of N N photon triggers, πίρ'.ο'Ό one effective memory 'blog about the device, a computer, a synchronization circuit, a trigger mode, controlled clock, ring shift register, clock divider by N and address dd counter, and the output of the single-electron pulse discriminator is connected to the first inputs of photon triggers, the second inputs of which are connected to the outputs of the ring shift register , output5, the synchronization circuit output is connected to the first input of the mode trigger, the output of which is connected to the input of the controlled clock generator and to the first input of the controlled first random access memory, the information outputs of which are connected to the computer input register, the output of the controlled clock generator is connected to the inputs of the ring register 55 shift and a clock frequency divider by N, the output of which is connected to the input of the address counter of words, the control output of which is connected to the second input of the mode trigger, with 7 and 7, which, in order to improve accuracy, are introduced into it an N-bit register temporary data storage, an OR logic element, a reversible counter and a second random access memory, and the outputs of the photon triggers are connected to an N-bit register of temporary data storage, the outputs of which are connected to the N first control inputs of the first opera main memory and to the N inputs of the OR gate, the output of which is connected to the forward counter input of the reverse counter, to _the second control input of the first random access memory, to the first control input of the second random access memory, the second control input of which is connected to the output of the mode trigger, the control output of the reverse counter is connected to the input register of the computer, the output register of the computer is connected to the input Count back of the reverse counter, the information outputs of which are lyucheny adresnvch to the inputs of the first and second random access memory, the address outputs of the address counter are connected to the data inputs of second random access memory, data outputs of which are connected to the input register of a computer.