SU1517107A1 - Method of stagewise control of speed of induction motor with thyristor switchgear - Google Patents

Abstract

The invention relates to electrical engineering and can be used to control electric drives of general industrial mechanisms, in particular, mine scraper conveyors, when powering electric motors with a quasi-sinusoidal voltage of reduced frequency. The aim of the invention is to simplify by forming stresses when switching an engine with a fixed lower speed to a nominal speed. The device for implementing the method contains a thyristor switch 1, a driver 9 clock pulses, a timer 10, logic elements 2I 11-25, 3I 26, 27, 4I 28, 2 OR 29-31, 3 OR 32, 3 OR-NOT 33, 4 OR 34, 35, divider 36 frequencies, pulse distributor 37, ring pulse distributor 38, galvanic isolation unit 39, differentiation circuit 40 and switches 41, 42. The proposed method and device for its realization allows, in a relatively simple implementation, to ensure a stepped start of the engine with frequency ratio F _s / F _m = 7

F _with / F _m = 4

F _c / F _m = 3, where F _c is the network voltage frequency, F _{m is the} frequency of the modulating voltage. 3 il.

Description

cl

ate

The simplification is due to the formation of stresses when switching the engine with a fixed lower speed to the nominal speed. The device for implementing the method contains a thyristor switch 1, a driver 9 clock pulses, a timer 10, logic elements 2I 11-25, ZI 26, 27, 4I 28, 2ILI 29-31, ZILI 32, ZILI-NE 33, 4ILI 34, 35, divider 36 frequencies, valve 37

w pulses, ring dispenser 38 pulses, galvanic isolation unit 39, differentiation circuit 40 and switches 41, 42. The proposed method and device for its implementation allow a relatively simple implementation to provide a stepped engine start with frequency ratio f, fc / f "4 ; fc / f.3, where fe is the frequency of the network voltage, the frequency of the modulating voltage. 3 il.

The invention relates to electrical engineering and can be used to control electric drives of general industrial mechanisms, in particular, mine scraper conveyors, when powering electric motors with a quasi-sinusoidal voltage of reduced frequency.

The aim of the invention is to simplify due to the formation of stresses when switching an electric motor with a fixed reduced speed of rotation to a nominal frequency of rotation.

FIG. 1 shows a structural diagram of the device for implementing the method of stepwise regulation of the frequency of rotation of an asynchronous electric motor.

bodies with thyristor switch; in fig. 2 is a diagram of a sync pulse generator; in fig. 3 - time diagrams for the device operation.

The device (Fig. 1) for implementing the method of step-by-step frequency control of an asynchronous electric motor contains a thyristor switch 1 consisting of three pairs of anti-parallel connected thyristors 2-7 connected between the supply terminals and the stator windings of the asynchronous electric motor 8, the driver 9 synchronizing pulses, timer 10, fifteen logical elements 2 And 11-25, two logical elements 3 And 26 and 27, logical element 4 And 28, three logical elements 2 OR 29-31, logical element 3 OR 32, logical element 3 Hilti NOR 33, two logical elements that 4 or 34 and 35, frequency divider 36, pulse distributor 37, the distributor 38 an annular momentum

.-

0

five

0

five

,

0

0

five

ow, block 39 galvanic isolation, differentiating circuit 40, two switches 41 and 42.

The outputs of the imaging unit 9 sync pulses and the timer 10 are connected to the power supply terminals, the first - the sixth outputs of the imaging unit 9 pulses are connected respectively to the first inputs of the first - sixth logic elements 2 And 11-16, the outputs of which are connected to the corresponding first inputs of the galvanic isolation unit 39, the second the inputs of which are connected to the outputs of the tenth-fourteenth and sixteenth logic elements 2 and 20-25, the outputs of the galvanic isolation unit 39 are connected to the control inputs of the thyristor switch 1. The seventh the output of the driver 9 clock pulses is connected to the counting input of a frequency divider 36, the zeroing input of which is connected to the output of the first logical element 4 OR 34, the first and second inputs of which are connected to the outputs of the eighth and ninth logical elements 2 and 18, respectively. The eighth and ninth outputs of the driver 9 sync pulses are connected to the first inputs of logic element 4 AND 28 and the first logic element 3 AND 26, respectively. The first and second outputs of timer 10 are connected to the second input of the first logic element 3 AND 26 and the first input of the second logic element 3, respectively And 27. The third and fourth outputs of the timer 10 are connected to the first inputs of the first 41 and second 42 switches, respectively, the second inputs of which are intended to give feedback commands. The outputs of the first and second switches are connected respectively to the first input of the seventh logical element 2 And 17 and the second input of the logical element 4 And 28, The second inputs of the seventh logical element 2 And 17 and the second logical element 3 And 27 are combined and connected to the output of the differentiating circuit 40. Outputs the first and second logic elements 3 And 26 and 27, the seventh logical element 2 And 17 and logic element 4 And 28 are connected to the corresponding inputs of the second logic element 4 OR 35, the output of which is connected to the clocking input at the distributor 37 pulses, the first output of which is connected to the third input of the first logic element 3 And 26, the second output of the distributor 37 of pulses is connected to the third input of the second logical element 3 And 27 and to the first inputs of the tenth and fourteenth logic elements 2 And 20 and 24, first to third logical elements 2 OR 29-31, logical element 3 OR 32 and logical element 3 OR-NOT 33. The third output of the pulse distributor 37 is connected to the third input of the logical element 4И 28, the first input of the ninth logical element 2 And 19, the second inputs of the first and third logical elements 2 OR 29 and 31, the logical element 3 OR 32 and the logical element 3 OR-NOT 33. The fourth output of the distributor 37 pulses connected to the first input of the eighth logical element 2 And 18 the second input of the second logical element 2 OR 30 and the third inputs of the logic element. 3 OR 32 and a logic element 3 WN-HE 33, the output of which is connected to the zero input of the ring distributor 38 pulses and the third input of the first logical element 4 OR 34. The fifth output of the distributor 37 pulses is connected to the input of the stop of the distributor 37 pulses and the second inputs first to sixth logic elements 2 and 11-16. The first inputs of the eleventh, thirteenth and fifteenth logical elements 2 And 21-23 and 25 are connected to the outputs of the first and third logical elements 2 OR 29-31 and the logical element Z.IL 32. The second inputs of the tenth-nth-eleventh logic elements 2 and 20-25 are connected respectively with

.l j 20 25 zo 4Q .c JQ

35

five

Vyma-sixth outputs of the ring distributor 38 pulses, the first and sixth outputs of which are additionally connected respectively to the input of the differentiating circuit 40 and to the fourth input of the logic element 4 And 28. The first output of the frequency divider 36 is connected to the clock input of the ring distributor 38 pulses, the second - the fourth outputs of the frequency divider are connected respectively to the second inputs of the eighth and ninth logic elements 2 and 18 and 19 and to the fourth input of the first logic element 4 OR 34.

The synchronization pulse shaper 9 contains (Fig. 2) a three-phase transformer 43, six comparators 44-49, six differentiating circuits 50-55, a logic element 6 OR 56. The inputs of the comparators 44-49 are connected to the secondary windings of the three-phase transformer 43, the primary windings of which form the inputs of the imaging unit 9 clock pulses. The outputs of the comparators 44-49, which form the first-sixth outputs of the imaging unit 9 clock pulses, are connected to the inputs of logic element 6 OR 56, the output of which forms the seventh output of the imaging unit 9 synchronizing pulses, the outputs of the second and sixth differentiating circuits 51 and 55 form the ninth and eighth outputs of the driver 9 clock pulses, respectively.

A device for implementing the method of stepwise speed control of an asynchronous electric motor with a thyristor switch operates in the following way.

During the formation of a three-phase system of modulation voltages, whose frequency is given by the ratio f ../ f 7 (k

L fn

1) in the initial state, the first outputs of the frequency divider 36, the pulse distributor 37, the ring distributor 38 pulses are set 1 at their remaining outputs O. Therefore, the O levels defining level 1 are fed to the inputs of the logic element 3 OR output supplied to the zeroing input of the ring distributor 38 pulses and through the logic element 4 OR 34 to the zeroing input

divider 36 frequencies. This prohibits the switching of the frequency divider 36 and the ring distributor 38 pulses.

Three synchronous pulses of the network frequency f j are applied to the input of the synchronizing pulses 9. Six comparators 44-49 of the former 9 form rectangular pulses that coincide with the areas exceeded by instantaneous values of the phase voltages: A, B, C, B, C, A of the instantaneous values of the phase voltages, respectively, B, C, A, A, B, C. These pulses enter the first to sixth outputs of the former 9 synchronizing pulses and the differentiating circuits 50-55 C of the outputs of the last pulses of limited duration coinciding with moments of equality mg The new values of the voltages of the two phases of the three-phase network are fed to the logical element 6 OR 56, From its output a sequence of pulses and, as shown in Fig. 3, frequencies of 6 fc are fed to the counting input of frequency divider 36. The input of the timer 10 also provides the network voltage. When occurrence 1 on the first output of timer 10, the pulse synchronized with the mains voltage (for example, with the equality of the instantaneous values of the voltages U and Uc in the positive region), taken from the ninth output of the imaging unit 9 synchronizing pulses, will go through logical elements 3 and 26, 4 or 35 to the clock input of the distributor 37, transferred 1 from its first output to the second. This will determine the effect of O at the inputs of zeroing the frequency divider 36 and the ring distributor 38 pulses. At the same time, 1 is established at the second inputs of logic elements 2 AND (20-25).

The fourth output of the frequency divider 36 is connected via logic element 4 OR 34 to the zeroing input of this same divider. Therefore, divider 36 divides the frequency of synchronizing pulses and into seven (transferred to the initial state by each eighth pulse). From the output of divider 36, pulses u4 (Fig. 3) with a following frequency seven times lower than the frequency of pulses U are fed to the clock input. the ring distributor 38, Its output pulses through the logic elements 2 and 20-25

arrive at the corresponding inputs of the galvanic isolation unit 39, where they expand three times and come in the form of unloading pulse packets (Fig. 5) to the thyristor control circuit 2-7 of switch 1,

The pulses form a three-phase system of modulating voltages, the frequency of which f, is given in the ratio, (f / f 6k-i-l when). In this case, the thyristors of the anode group 2, 4 and 6 are supplied with pulses Uj, Uj and, respectively, corresponding to the positive polarity of the modulating voltages, and the thyristors of the cathode group 3, 5 and 7 are supplied with pulses U, U and Ug, respectively, corresponding to the negative field modulation voltages. In FIG. 3 — the EMF of self-induction of the rotor of the engine (e, ep, e J. are shown in dotted lines). Coincide with the modulation voltage.

Thus, a three-phase system of quasi-sinusoidal voltages (Uj ,, and, and) of a lower frequency is formed at the output of the commutator. When a command appears on the second output of timer 10 to switch the modes of the electromotor motor 8 (level 1) after the next channel (for example, the sixth) ring distributor 38 pulses at the time C expires, the pulse of limited duration from the output of the differential circuit 40 through the logic elements 3 And 27, 4 OR 35 enters the clock input of the distributor 3 pulses, transfer 1 from its second output to the third. This prohibits the supply of control signals to the galvanic isolation unit 39 from the first, third, and fifth outputs of the ring distributor 38. In this case, the ring distributor 38 forms alternating inhibitory and permissive signals. The latter are removed from the second, fourth and sixth outputs of the ring distributor 38 and through the logic elements 2 OR 29 and 31, 3 OR 32, as well as 2 AND 21, 23 and 25 and the galvanic isolation unit 39 are applied to the thyristors control circuits 2-7 of the switch 1, at the same time, level 1 is set at the first input of element 2 and 19, the division factor of divider 36 is determined to be four. Level 1 is set at the third input of logic element 4 And 22, allowing the next control command to be sent to the input of the distributor 37 pulses. Thus, the frequency of the modulating voltage is reduced by 4 times compared to the frequency of the network voltage f and, in so doing, alternate inhibitory and permissive signals (beginning with prohibiting) each length - 1 2

4 "

6f,

3f.

(insofar as

 with

the duration of the pulse removed from each of the six outputs of the ring

distributor 38 is 77-

In this case, the control pulses from -Ug are fed to the corresponding thyristors of the switch 1 at intervals of the existence of the enabling signals. In this case, pulses Uj, L, and, on the fourth, pulses Uj, and Uj, are generated at the second output of the ring distributor, and pulses of and, and for ultrasonic (time interval, FIG. 3) are at the sixth. This achieves a smooth increase in the frequency of rotation of the rotor of the engine 8, which is reflected by a change in the EMF curves of self-induction of the rotor. The latter in FIG. 3 coincide with the modulating voltages that form the curves of the phase quasi-sinusoidal voltages. At the time of the formation of each successive pulse at the output of the ring distributor 38, the polarity of the corresponding modulating voltage changes.

The pulses are applied to the thyristors 35 at intervals of the existence of the enabling signals. At the same time, the sinus sections of the network network voltage, preceding the time D, are formed at the moment when the prohibitive signal is terminated. At the next command at the modulation frequency f, the corresponding increase in the rotor speed of the electric motor (level 1 at the fourth output of timer 10 or level 1 at the second input of the switch 42, when using feedback commands for the frequency of rotation of the electric motor), level 1 is fed to the second input of logic element 4 AND 28. The first and fourth inputs of the logic element are supplied continuously from the eighth output shaper 9 and the output from the sixth annular distributor 38. At time f simultaneous arrival of signals at all inputs of NAND gate 4 and 28 its output level 1 is supplied through the OR gate 4 to 35

clocking input of the distributor 37, I) 111

carry

 R

its third ratio and simultaneously belong to the modulation voltage of this frequency and the modulation frequency f

45 f (. This allows you to smoothly increase the frequency of rotation of the rotor of the electric motor 8 to the level corresponding to a given frequency of the modulating voltage (in the area f j of Fig. 3).

50 In this case, at the time of the occurrence of each successive pulse, at any of the outputs of the ring distributor 38, the polarity of the corresponding modulating voltage, coinciding with the rotor EMF shown in FIG. 3

|.

When receiving the command to file

to the motor 8 voltage network

ten

fourth. Level logical inputs

R

ten

the stroke is applied to the elements 2 of the IPI 30 and 3 IPI 32, allowing the thyristors 2-7 of the switch 1 of the control signals to be supplied through the galvanic isolation unit 39 from the third and sixth outputs of the ring distributor 38. This determines the ratio of the durations of alternating inhibiting and enabling signals like 2: 1. With this impulses

and

3

formed by a signal with

25

the third output of the ring distributor is 38, and the pulses U, Us and U are from the sixth output. Level I is fed to the input of the logical element 3 OR-NOT 33, allowing the operation of the divider 36 and the frequency of the ring distributor 38 to the first input of the logical element 2 and 18, setting the division factor of the divider 36 to three.

Thus, at the moment of changing the polarity of one of the modulating voltages, the frequency of the latter is reduced by three times compared to the network voltage fc and, in so doing, alternate inhibiting and resolving signals are formed. The duration of the enabling signals is set to 3 "

13

i-y-y, and prohibiting,. Manage-

L impulses are applied to thyristors 35 at intervals of existence of the enabling signals. At the same time, the segments of sinusoidal voltage of the network preceding the moment D ,, are formed at the moment of the end of the prohibitive signal at the modulation frequency f of the correlation at the modulation frequency f of the ratio and belong simultaneously to the modulation voltage of this frequency and the modulation frequency subsequently formulated f ratio

45 f (. This allows you to smoothly increase the rotor speed of the electric motor 8 to the level corresponding to the given frequency of the modulating voltage (in the area fj of Fig. 3).

50 In this case, at the time of the occurrence of each successive pulse, at any of the outputs of the ring distributor 38, the polarity of the corresponding modulating voltage, coinciding with the EMF of the rotor, shown in FIG. 3

|.

When receiving the command to file

to the motor 8 voltage network

(level 1 at the third output of timer 10 or level 1 at the second input of switch 41) level 1 is fed to the first input of logic element 2 AND 17. At the end of the cycle of operation of the ring distributor 38 at the time of € j, level 1 goes to the clock input of the distributor 37 transfer level 1 from its fourth exit to the fifth. This prohibits the supply of galvanic isolation of the output pulses of the ring distributor 38 to unit 39. The absence of levels 1 at the second to fourth outputs of the distributor 37 determines the occurrence of level 1 at the output of the logical element 3 OR-HE 33 and the supply of this level to the zeroing inputs the divider 36 and the ring distributor 38 pulses, prohibiting their operation. The formation of push-pull voltages at the output of the switch 1 is terminated. At the same time, level 1 is fed to the stop Q input of the distributor 37, stopping the process of transferring commands to its outputs, and to the second inputs of logic elements 2 AND 11-16, allowing the supply of rectangular control pulses from the first six outputs of the driver 9 to the galvanic isolation unit 39

In this case, the electric motor 8 is supplied with the mains voltage.

Thus, when controlling an electric motor according to the proposed method, the process of forming a voltage of lower fixed frequencies and switching the motor in a rotating state from a source of quasi-sinusoidal voltage of a lower frequency to a three-phase network is simplified.

Claims (1)

Claim method A stepwise frequency control of an asynchronous motor with a thyristor switch, in which the first, second and third modulating voltages are formed, respectively, forming a three-phase system with a fixed frequency corresponding to a given frequency of rotation of the motor and determined from the ratio fj / f bK + 1, control pulses are supplied for the thyristors of the anode group of the switch when the polarity of the respective modulating voltages is positive, and for the thyristors of the cathode group of the switch when the polarity of the corresponding modulating voltages is negative, characterized in order to simplify due to the formation of voltages when switching an electric motor from a fixed lower frequency of rotation to the nominal frequency of rotation, at a given frequency of modulating voltage in the ratio, the moment of change neither the polarities of any of the modulating voltages and from this moment set the frequency of the modulating 0 voltages in the ratio, they form alternating inhibiting and enabling pulses, each 2 five value 3fc starting with a prohibiting signal, and supplying control pulses to the corresponding switch thyristors at intervals of existence of the enabling pulses, after a corresponding increase in the rotation frequency of the electric motor during the existence interval of the enabling pulse, the time moment is determined from the beginning of the enabling pulse by 1/2 fp and synchronized with at the request of the network, and from this point on, set the frequency of the modulating voltage in the ratio f ,, form alternating locking and enabling pulses, starting with present and setting the duration of the inhibiting pulses to 1 / f j. For the duration of the enabling pulses, equal to I / 2f (., and the control pulses are fed to the corresponding thyristors of theNryTaTopa at the intervals of the existence of the enabling pulses, and after a corresponding increase in the rotation frequency of the electric motor, the polarity of any of the modulating voltages and supply a three-phase voltage of the mains frequency to the electric motor, where fc is the mains voltage, m is the frequency of the modulating voltages, –K - I, 2, 3 ... the number of natural p yes. mmmmmmmsmsmsmmmmmmmsmsm: (/four /, T | L V7 D V l t to . . VJl / M I IK  .r t 2 i.j L / I-J t.  four It ill i ftp -w z to  I IK   t. / r i 1 kshi 11 / T, I, Fig.Z