SU1288856A1 - Control device for three-phase semiconductor switching device for quasisine voltage - Google Patents

Abstract

The invention relates to electrical engineering and can be used to control a power semiconductor switch. The aim of the invention is to expand the functionality. At the output of the switch, a system of three-phase quasi-sinusoidal voltages of lower modulation frequency is formed, each half-wave of which consists of sinusoidal sections of network voltage. Depending on the magnitude of the control, phase regulation of the magnitude of the segments of these sinusoids is made and, therefore, regulation of the magnitude of the quasi-sinusoidal stresses. 2 il l S (L

Description

The invention relates to electrical engineering and can be used to control a power semiconductor switch that forms a quasi-sinusoidal voltage of lower frequency to power an asynchronous electric drive of machines and mechanisms during operation at lower speeds with elevated starting electromagnetic moments.

The purpose of the invention is to expand the functionality by implementing phase control of the output quasi-sinusoidal voltage of a semiconductor switch.

Fig, 1 shows a diagram of the device; Fig, 2 - diagrams of the device.

The device (FIG. 1) consists of a node 1 of power thyristors and a control system, the node of power thyristors contains three pairs of three oppositely connected thyristors 3-8 connected between the power source and the load (drive motor) 2, the control system contains the synchronization pulse shaper 9, the input of which is connected to the network from the power supply side and the output to the clock input of the clock frequency divider 10, the i-th output of which is connected to the clock input of the six-channel ring pattern pulse divider 11, and (1-1) -th output is connected to synchronization input 12 of phase-shifting unit 13, Phase phase control input input 14 of phase-shifting unit 13 is connected to output of control voltage setpoint 15, and output 13 is connected to first scrub inputs elements And 16-21, the second inputs of these elements

connected to the outputs of the six-channel

the ring distributor 11 pulses, and the inputs to the corresponding channels of the amplifier-decoupling node 22. The inputs of this node are connected to the control circuits of the corresponding thyristors.

The synchronization pulse shaper 9 is designed to generate synchronization pulses, the frequency of which is six times higher than the mains voltage frequency. As the frequency divider 10, n-channel can be used.

five

-five

0 5 0

five

0

five

0

five

ring pulse distributor. The number of channels determines the frequency of the quasi-sinusoidal voltage

The device works as follows.

The clock input of the divider 10 receives synchronized 1e pulses (Uj, Fig 2) from the output of the driver 9, Their frequency is six times the maximum voltage frequency, and from the i-ro output of the divider 10, the pulses U are fed to the clock input of the six-channel ring distributor 11 pulses The outputs of the latter are pulsed, the duration of which is equal to three periods of operation of the divider 10 (half the modulation period of the output quasi-sinusoidal voltage of the switch), and at least can be equal to two periods

From the (i-l) -ro output of the divider 10, the pulses are fed to the synchronization input 12 of the phase shifting unit 13. The control voltage is supplied to the input 14 of the control of the phase of the pulse of the unit 13 from the output of the setting unit 15. Phase shifting 1st unit 13 generates a sequence of saw-tooth stresses and, s, each of which is formed during the time when there is no impulse and removed from (il) -ro of the output of the divider 10, these saw-like stresses and, s are compared with the values of control unit U, and, starting from the moment of equality of these voltages until the sawtooth voltage is completed, rectangular pulses form and are fed from the output of block 13 to the first inputs of six logic elements AND 16-21 and allow the passage of pulses Uy, -Uyg, with imaemyh output from the distributor 11 and fed to the second input element. And 16-21, the duration of the pulses U, -U, taken from the outputs of the elements And, is determined by the duration of the pulses and supplied to the first inputs of the elements And 36-21 and depends on the magnitude of the control voltage C,

Each of the impulses U - and

enters through the corresponding channel of the output amplifier-p of the calling node 22 to the control input of the corresponding thyristor 3-8 of node 1,

The power thyristors unlocked in this way form 3-8 at the output of node 1 of the switchboard of a system of three-phase quasisinusoidal voltages

(and

reduced modulation frequency

and and). Each half wave of this

J

The quasi-sinusoidal voltage consists of sinusoid sections of the network voltage. Depending on the magnitude of the control voltage, phase adjustment of the sections of these sinusoids is performed, which means

and regulation of magnitude

quasi-sinusoidal stresses U, u, and U.

BUT

The angle of adjustment d. The sinusoid sections of the network voltage are within the limits of an f-d 240 el. hail, for an average segment of a sinusoid at half-wavelength of a quasi-sinusoidal voltage and Oo (. 4,180 electr, hail, for the remaining intervals of sinusoids, a half-wave of quasi-sinusoidal voltage.

Claims (1)

Invention Formula A device for controlling a three-phase semiconductor switch of quasi-sinusoidal voltage. yarn, it is equipped with cops And phase shifting 15 synchronization inputs of the phase of the pulse, setting voltage, and the bias block of the connection of six elements And, second 20 of them are connected to the co-outputs of the six-channel distributor impulse to the inputs of the amplifier-p node, the input is synchronized The 25th block is connected to the output of the frequency division of the steering pulses, the output of the control voltage of the control phase input containing the synchronization driver 30 phases of the bias block. 2888564 pulses, the frequency divider synchronizing pulses, the i-th output of which is connected to the input of the sixth ring ring distributor of 5 bodies of pulses, the output amplifying-decoupling node, the output of which is intended for connection to the control inputs of the switch, which differs from , 10 in order to expand the functionality, by implementing phase control of the output voltage, it is equipped with six AND elements, a phase shifting unit with synchronization and phase control pulse inputs, a control voltage setting unit, the output of the phase-shifting unit is connected to the inputs of six elements And, the second inputs of which are connected to the corresponding outputs of the six-channel ring distributor of pulses, and the outputs to the inputs of the amplifying node, the input sync phase shifting the control unit is connected to (1-1) -th output of the frequency divider of synchronizing pulses, the output of the control voltage setting device is connected to the input of the control of the phase of the pulse 74 ten . Lui -TO sixteen AND 17 J8 ten eleven 19 20 21