SU1515295A1 - Device for controlling bridge-type transistor inverter - Google Patents

Abstract

The invention relates to electrical engineering and can be used to control secondary power supply sources. The purpose of the invention is to increase the reliability of control in the process of stabilizing the output voltage of the inverter. The device is based on blocks of 1 and 6 formation of time intervals of fixed and variable duration, block 10 of distribution of time intervals of variable duration over time intervals of fixed duration, switch 17 and trigger drivers 16 and 24, respectively, of low-frequency and high-frequency control pulses for transistors 28,29 and 30 , 31 inverters 27. The first of the mentioned signals are symmetric, rectangular, and the second are width-modulated with alternating sinusoidal and (1-SIN) -th order modulations. Due to the introduction of analog-digital converter 34, controlled frequency divider 7, block 6, all necessary switching of functional units during operation of the device is carried out with frequencies strictly synchronized with the master frequency of the pulse generator 2 included in block 1. This eliminates parasitic frequency beats and faults in the inverter control circuits 27. Connecting the clock input of the feedback node 33 to one of the outputs of the trigger shaper 16 of the low-frequency control pulses also allows do without an additional pulse generator when stabilizing the rms value of the inverter output voltage. 1 hp f-ly, 3 ill.

Description

S 1 (L

ate

SP

to

WITH

ate

HMf

3151

the devices make up I and 6 blocks of fixed and variable duration time intervals, block 10 of variable time interval distribution over fixed time intervals, switch 17 and trigger drivers 16 and 24, respectively, of low-frequency and high-frequency control pulses for transistors 23,29 and 30.31 of the inverter 27. The first of the mentioned signals are symmetric, rectangular, and the second are width-modulated with alternating sinusoidal I1 / 1-81p / -m law s modulation. Thanks to the introduction of the analog-digital converter 34,

five

controlled frequency divider 7, block 6, all necessary switching of functional units during operation of the device are carried out with frequencies rigidly synchronized with the driving frequency of the 2-pulse generator included in block 1. This eliminates parasitic beats and faults in the inverter control circuits 27 Connecting the clock input of the feedback node 33 to one of the outputs of the trigger generator I6 of low-frequency control pulses

It also eliminates the need for an additional pulse generator to stabilize the rms value of the inverter output voltage. 1 hp f-ly, 3 pp.

The invention relates to electrical engineering and can be used in the implementation of secondary power supply sources.

The aim of the invention is to increase the reliability of control in the process of stabilizing the output voltage of the inverter.

In fig-. 1 is a functional block diagram of a device for controlling a transistor bridge inverter; figure 2 - timing charts of the signals at the outputs of the nodes; FIG. 3 is a diagram of a feedback node.

The device contains a block 1 of forming p time intervals of fixed duration with a series-connected pulse generator 2, a clocking trigger 3, a counter of 4 pulses and the first decoder 5, a block 6 of forming p / 2 time intervals of variable duration with a series-connected controlled divider 7 frequency , a reverse pulse counter 8 pulses, the control inputs of the forward and reverse counts of which are connected to the corresponding outputs of the clock trigger 3, and the second decoder 9, block 10 the time intervals of variable duration in the time intervals of a fixed duration with gating elements 1I.1-11. And, of which the first n / 2 elements are connected by inputs with

five

ABOUT

Q d 50.

the same outputs of the decoders 5 and 9, and the inputs of each i-ro from the second n / 2 elements are connected to the same output of the decoder 5 and (n-1 +) to the th output of the decoder 9 by two groups of distribution elements 12.1-12.n and 13.1-13 .PI, the first inputs of which are connected to the codes of the same gating elements 11.1-11.PI, and the second inputs - to the direct and inverse outputs of the clock trigger 3, the first and second elements 14 and 15 OR, the inputs of which are connected to the outputs of the distribution elements 12.1 - 12.p and 13.1-13.p. And, the trigger driver 16 or Frequency control pulses, the input of which is connected to the first output of the decoder 5, the switch 17 with two pairs of channel elements 18 and 19 and 20 and 21 AND, in each of the pairs the first input of one element AND is connected to the direct one, the first input of another element I - to the inverse outputs of the trigger shaper 16 low-frequency control pulses, and their second inputs to the outputs, respectively, of elements 14 and 15, the third and fourth elements 22 and 23 OR, the inputs of each of which are connected to the outputs of the channel elements 18,19, 20 and 21, respectively , three Gurney driver 24 controlling high-frequency pulses, the inputs of which are connected to

the elements 22 and 23, the output power amplifiers 25 and 26, the outputs of which are connected to the direct and inverse outputs of the trigger drivers 16 and 24 of the low-frequency and high-frequency control pulses, and the outputs are intended for connection to the emitter-base transitions of the incoming Inverter 27 includes transistors d 28 and 29, 30 and 3, forming a bridge with a 32 low-pass filter in a diagonal, feedback node 33, the input of which is connected to the outputs for connecting to

the output of the inverter 27, the clock input of the node different from each other in order 33 is connected to one of the outputs of the low-frequency control trigger generator 16, the analog-to-digital converter 34, the input of which is connected to the output of the node 33, corresponds to a clock duration of 20

follow the intervals of a sinusoidal law. If, in particular, n 16 and, therefore, the angular range of one time interval is fixed

Connect the input to the output of the generator 2 connected to the clock input of the controlled divider 7, and the output to the control input of the latter.

Feedback node 33 is represented by. It is a pulse-compensated converter of the rms value of alternating voltage to constant, implemented according to the scheme with direct and inverse quadratures 35 and 36 on field-effect transistors, integrator 37 and modulator 38 (FIG. 3). In this case, the functions of the generator of modulating pulses are performed by generator 2 of block 1.

The device works as follows.

Each of the n outputs of block 1 produces pulses U1 of equal duration (Fig. 2a), the total duration of which, within the period of operation of block 1, corresponds to half of the required period T of the surge voltage of the inverter 27. In principle, n can be chosen as even and odd, which ultimately causes a very small difference in the spectral composition of the output voltage. From practical considerations, taking into account the widespread use of elements of computing equipment operating in binary code, it is more convenient to select evenly common intervals of n intervals for a cycle over a fixed time interval.

for example, 16 (however, for the duration, the time-consuming diagnostic function node is, in essence, of great loyalty, and t) the frames of FIG. 2 are shown for the case of the indicated distribution

odd n). under the action of signals from the outputs Tc. The stability of the period T of the output voltage of the inverter 27 is determined by the stability of the total duration of the intervals, which is maintained at a high level due to the presence of a stable frequency generator 2 in block 1.

The operation of block 6 is based on a priori selection for a set of n time intervals of a fixed duration of a set of n- (two sets of n / 2) gradations, i.e. p yes of natural numbers differing from each other in the order of sirovanny duration corresponds to

follow the intervals of a sinusoidal law. If, in particular, n 16 and, therefore, the angular range of one time interval is fixed

11 ° 15, then for the angles belonging to the midpoints of the intervals, one can choose the following numerical series: 3,8,13,18, 22,25,27,28,27,25,22,18,13,8,3 . The maximum number in the row (28) characterizes the accuracy of approximation of the specified set of gradations to the sinusoidal law in nominal mode (maximum load mode)

O of the inverter 27 and is limited by the total number of outputs in the decoder 9 of block 6, by means of which the values of the numbers of the selected row are fixed.

The durations corresponding to the recorded gradations are formed by the reversible counter 8 included in block 6, which, under the influence of signals from the outputs of the clock trigger 3, in the second half of each interval of a fixed duration performs the summation of pulses from the output of the controlled divider 7, and in the first half their subtraction. As a result, during each interval of a fixed duration, on all outputs of block 6 (decoder 9), pulses appear twice (Fig. 2b). The time interval between the remote control I1-L1UL; themselves on that or 1shig output of block 6 characterizes the formed duration.

Block 10 of the distribution of time intervals of variable duration

five

0

1 1515295

of the triggering trigger 3. The time intervals between the pulses and and 1 arranged in intervals of a fixed duration, and 1 (Fig. 2, c) change

and; and 1: dfig.2, c)

from interval to interval sinusoidally.

The trigger shaper 16 low-frequency control pulses, using signals from the first output of the decoder 5, generates symmetric rectangular signals U, and U (figure 2, d), shifted relative to each other by 180. These signals are from 10

pu pa about us and pr sign

la w te

are used to control the transistor for successive pulse counting from

generator 2 of block 1 is converted to binary code. The code formed in the analog-to-digital converter 34 automatically selects the division factor in the controlled divider 7, which receives pulses from the generator 2.

25

28 and 29 of one of the branches of the inverter 27 and control the switch 17 with the output voltage frequency. The latter separates the pulses formed at the outputs of the block 10 20 and Jo and o into two sequences and feeds them to the inputs of the trigger shaper 24 high-frequency control pulses (in the time diagrams of FIG. 2, the indicated pulse sequences are not displayed).

The trigger driver 24 high-frequency control pulses, perceiving signals from the spin codes of switch 17, ultimately reproduces latitude-modulated signals U ,, and U24 (FIG. 2, e) with alternating T / 2 impulse sets modulated according to different laws. . One of the sets of pulses has a sinusoidal modulation law (pseudosinusoidal signal), and the other is (1-z1n) -th law. Signals and.

thirty

35

24

and

one

generator 2 of block 1 is converted to binary code. The code formed in the analog-to-digital converter 34 automatically selects the division factor in the controlled divider 7, which receives pulses from the generator 2.

When the rms value of the output voltage deviates from the nominal value under the influence of various destabilizing factors, the DC voltage level at the output of node 33 changes in the appropriate direction, the binary code at the output of converter 34 and the division factor in the controlled divider 7 of block 6 As a result, the counter input of the reversal counter 8 pulses arrives faster or slower, the time intervals between the pulses U change (shorten or lengthen) (ph D.2, b), taken from the same block outputs

are used to control transistors | 0 6 (decoder 9), and between pulses 30 and 31 of inverter 27, at the output of which low pass filter 32 results in a sinusoidal voltage (Figure 2, e),

The power amplifiers 25 and 26, in addition to 45 MO of the control signal amplification, provide the required galvanic isolation of all four control circuits.

The feedback node 33 senses the sinusoidal voltage from the output of the filter 32 of the inverter 27 and converts it into a constant voltage Ujj proportional to the root-mean-square value of the output voltage j or the inverter.

The operation of the modulator 38 with the switching frequency of the trigger shaper 16 low-frequency transducers and Jo and Uj o (Fig. 2, c) at the outputs of block 10 related to the same intervals of fixed duration, as well as the duration of the width-modulated signals 24 t (FIG. 2, d) at the outputs of the trigger generator 24 while maintaining the sinusoidal and (l-sin) -ro laws of modulation. Since the durations of the first harmonics in the frequency spectrum of the output voltage U of the inverter 2 depend on the durations of the pulses making up the signals U j and Uj, this automatic control process stabilizes the RMS value at this level.

The analysis of the device operation shows that in this case everything is necessary.

control pulses, i.e. with a frequency equal to the frequency of the voltage of the feedback node 33 arriving at the signal input, provides identical operating conditions for forward 35 and reverse 36 squares and thereby determines an increased accuracy of the conversion of the rms voltage.

The constant voltage from the output of the feedback node 33 is fed to the input of the analog-digital converter 34, where the following pulse counting method from

25

20

thirty

35

generator 2 of block 1 is converted to binary code. The code formed in the analog-digital converter 34 automatically selects the division factor in the controllable divider 7, which receives pulses from the generator 2.

When the rms value of the output voltage deviates from the nominal value under the action of various destabilizing factors, the DC voltage level at the output of the node 33 changes in a corresponding direction, the binary code at the output of the converter 34 and the division factor in the controlled frequency divider 7 of block 6. As a result, pulses go to the counting input of the reversing counter 8 faster or slower, the time intervals between the pulses change or increase accordingly. E U (2, b), removable with the same output block

t | 0 6 (decoder 9), and between the pulses

6 (decoder 9), and between the pulses

Jo and Uj o themselves (Fig. 2, c) at the outputs of block 10, referring to the same intervals of fixed duration, as well as the duration of width-modulated signals 24 t (Fig. 2, g) at the outputs of the trigger former 24 while maintaining the sinusoidal and (l-sin) -ro modulation laws. Since the duration of the first harmonics in the frequency spectrum of the output voltage U of the inverter 27 depends on the durations of the pulses that make up the signals U j and Uj, this automatic control process stabilizes the RMS value at a predetermined level.

Analysis of the operation of the device shows that in this case all the necessary switching of the composite nodes is carried out with frequencies strictly synchronized with the clock frequency of the generator 2 included in block 1. This applies, in particular, to the feedback node 33 and to the analog-to-digital converter 34, and mainly to the controlled divider 7 of the frequency of block 6, the formation of fixed and variable durations in the belt intervals at the outputs of blocks 1 and 6 is thus produced without failures in the inverter control circuits 27, which ensures the increased reliability of the control of the stabilization process of the output voltage of the inverter-27 and, moreover, allows us to obtain a higher} quality of stabilization of the root-mean-square value of the voltage due to the increased conversion accuracy.

Claims (1)

1. A device for controlling a transistor bridge inverter, comprising a block of forming n time intervals of fixed duration, consisting of a series-connected pulse generator, a clocking trigger, a pulse counter and the first decoder with p codes, a block of forming p / 2 time intervals of variable duration consisting of a series-connected reversing pulse counter, the control inputs of the forward and reverse counts are connected to the inverse and forward outputs of the clock the second trigger, and the second decoder with p / 2 outputs, the block of distribution of time intervals of variable duration over time intervals of a fixed duration, containing n gating elements, the inputs of the first n / 2 gating elements And are connected to the same outputs of the first and second decoders, inputs. each i-ro and second p / 2 gate elements I are connected to the same output of the first decoder and () the second output of the second decoder, two groups of π distribution elements I, the first inputs of which are connected to the outputs of the same gating elements AND, the second inputs of the distribution elements And the first and second groups are connected respectively to the direct and in u 15 20 25 so 35 40 five 0 five To the persistent outputs of the clock trigger, the first and second elements OR, the inputs of each of which are connected to the outputs of the distribution elements AND of the corresponding group, the trigger generator of the low-frequency control pulses, the input of which is connected to the first output of the first decoder, the switch containing two pairs of channel elements And, the third and fourth elements OR, in ktzhdy of pairs of channel elements AND the first input of one element AND connected to the direct, the first input of another element - AND - to the inverse outputs Tpiirrepuoi o f1 1rmirovitel izkochas totnyh imp / ls n control; second inputs to the outputs of the first and second element OR, inputs of the third and fourth elements OR connection to the outputs of channel elements AND the corresponding base, trigger generator of high-frequency pulse control, whose inputs are connected to the outputs of the third fourth elements OR, two r -shaking :; - power amplifiers, the inputs of which are connected to the direct and invariant outputs t; ch11ggern1-1x formers corresponding to the low-frequency and high-frequency control pulses, the outputs P1) are intended to connect to the input: -; a transistor bridge inverter, a feedback node, the input of which is intended to be connected to the transistor bridge inverter and the clock input is connected to the output of a triggers driver H1ik1 of four direct control pulses, so that In order to increase reliability in the process of stabilizing the output voltage of the inverter, it is equipped with an analog-digital converter, the form block — n / 2 time intervals of variable duration — is controlled by a frequency divider. An analog-to-digital converter input is connected to the feedback node of the feedback node, the clock inputs of the analog-to-digital converter and a controlled frequency divider are connected to the output, a pulse generator, and the outputs of the analog-to-digital voltage converter are connected to the control outputs of the control terminal. frequencies. 0 l / f fae. 2