SU1508332A1 - Device for stabilizing electric motor revolutions - Google Patents

Abstract

The invention relates to electrical engineering and can be used in automatic control systems. The aim of the invention is to increase speed and accuracy. The device contains two frequency dividers 14,15 with a variable division factor connected between the second and third outputs of the code-frequency converter 2 and the first 5 and second 6 elements, respectively. Two constant memory devices 12 and 13 connect the speed setter 1 to the installation inputs dividing coefficients of frequency dividers 14 and 15. The initial setup of the summing counter 17 through the first register 9 is connected to the output of the subtractive counter 7, and the inputs of both counters 7 and 17 are connected to the output of the first And 5 element. changing the given speed provides a constant for the angular and velocity error conversion coefficients, as well as measuring the speed error during one period of the feedback signal pulses. 2 Il.

Description

ate

about

OD CO 00

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The invention relates to electrical engineering and can be used to stabilize the frequency of rotation of electric drives in automatic control systems.

The purpose of the invention is to increase the speed and accuracy of the device.

FIG. 1 shows a diagram of the proposed device; in fig. 2 - converter code - frequency circuit.

The device contains a speed controller 1, a code 2 converter connected to it — a frequency — the first output of which is connected to one, and the speed sensor's 3 code (ID) of the speed — to another input of a frequency frequency-phase discriminator (ICFD) 4 connected to the first 5 and the second 6 And elements, the outputs of which are connected respectively to the inputs of the detracting counter 7 and the first summing counter, two registers 9 and 10, a digital-to-analog converter 11, the first 12 and second 13 permanent memories (ROM) connected by inputs to the task tick 1 speed, and outputs - with the inputs of setting the division coefficients of the first 14 and second 15 frequency dividers, with a variable division factor, connecting the first 5 and second 6 And elements, respectively, with the second and third outputs of the converter 2 code - frequency, block 16 the initial installation of the codes connected to the inputs of the initial installation of the detracting counter J and the first summing counter 8, the second summing counter 17, the input of the initial installation of which through the first register 9 is connected to the output of the deducting counter ika 7. and the counting input - with the output of the first element And 5, the adder 18.j whose inputs are connected to the codes of summing counters 8 and 17. And the output through the second, register 10 - to the input of the digital-analog converter 11. In this case, the inputs to the code entry of counters 7, 8 and 17 and registers 9 and 10 are connected to the output of the pulse frequency-phase discriminator 4.

The code-frequency converter 2 comprises a pulse generator 19, the output of which is connected to the inputs of frequency dividers 20 and 21 and a divider 22 with a variable division factor. The inputs for setting the division factor 22 of the divider 22 are supplied with a speed setting code N from the setpoint 1 speed.

The device works as follows.

The code N is fed to the input of the converter 2 from behind the speed sensor 1,

proportional to the set frequency of rotation of the electric drive. Converter 2 converts the code into a sequence of pulses with a frequency fj. The signal from the converter 2 is fed to one of the inputs of IChFD 4, the second input of which receives a signal from the pulse speed sensor 3. ICFD 4 generates at its output a pulse signal, the duty cycle of which

proportional to the angular error (phase mismatch between the pulses of the setpoint and feedback signals). The signal of the logical unit coming from ICFD 4 allows

passage of pulses f ah i f-f K; j, where f. - the frequency of the signal at the input of the divider 14 with a variable coefficient of the division volume K f, and f VC i V where f. - the frequency of the signal to the input divider 15 with a variable division factor K, respectively, through elements 5 and 6 to the inputs of subtractive 7 and summing 8 counters. Parish with. The discriminator 4 of the logical zero signal prohibits the passage of the pulsed signals f lm and f hcg through elements 5 and 6, with the result that the output of counters 7 and 8 forms a code proportional to the angular error and l If, where / 3 tf

  offset angle error

ka, Z is the number of ID tags.

At time t T., T.-

 2- (where

J - J- J) the contents of counter 8 is zero, and since t o it changes to

TO,.

Tz

2TGK.1

 TO

fgTj and K, -2

where Kj is the coefficient of proportionality; code-voltage; K is the division ratio of the divider 15 with a variable division ratio,

Thus, the signal at the output of the counter 8 is associated with the angle error signal 4t / 5 s D

u} is the set frequency of rotation of the drive, defined as follows:

fl-kf

N3K.cf

fg-Kf aif

J N,

-and

KiK, 1s

(. is the conversion factor for the angular error; the angular distance between the ID marks,

t / o 2ir-Z - 4tHV -

the offset angular error is obtained due to the constant displacement of the output signal of the discriminator 4 by f / Z,

When & L (About the value of the signal at the output of the counter 8 must be equal and therefore the initial content of the counter 8 is chosen equal to

„KuKdc Uo 2

whereby its output signal is equal to

dH d / WoT,

Pre-recording into counter 8 is performed in an additional code on the falling edge of the pulses of the output signal of the pulsed frequency-phase discriminator 4 fed to the C input. Counter 8 code is written. To maintain a constant value of the coefficient K q) of the angular error conversion,

± 2-,

fgKf .K-jN

 const,

.-one

where K ,, N-f, is the conversion factor-code-frequency.

This is ensured by the appropriate programming law of ROM 13, as a result of which the division factor of divider 15 (K,) changes when the speed setting code NJ changes in accordance with the dependence

In counter 7, the falling edge of the discriminator 4 pulse from block 16 of the initial code installation records the code corresponding to U 0 (in the additional code).

Output signal U, К „- df

counter 7 enters through register 9 to the input of the initial installation of summing counter 17, the output signal of which is proportional to the error in speed and equal to

 and

&,

- and

LS / C

TO

  (4Cf (K)), K- (to

KiklyM

l 00 (k),

25

where M is 1 s;

yso (K) is the error in speed at the Kth instant of time,

t

period of the reference signal at the output of converter 2

TO

BEFORE)

f T C- | g- conversion factor

  speed errors

Dp maintaining a constant conversion rate error rate in the whole range of control, the condition

45

This is ensured by the appropriate programming law of ROM 12, as a result of which the divider ratio 14 (Kf) of the division changes as

eg changing the speed reference code according to the dependency

f, Kf

to

4U)

The code from the output of the counter 17 is fed to one of the inputs of the adder 18, the second input of which receives the code from the counter 8.

Claims (1)

Claim A device for stabilizing the speed of an electric motor, comprising a speed adjuster, a frequency code converter connected to it, the first output of which is connected to one, and the output of a pulse speed sensor to other inputs of a pulse frequency-phase discriminator 35, the output of which is connected to the first inputs of the first and the second elements And, two registers, the first and second totalizing counters, the inputs of which are connected to the outputs of the second and first elements 5 And, respectively, a digital-to-analog converter connected to the output of the second register, characterized in. that, in order to improve performance and accuracy, the first and second frequency dividers with a variable division ratio are introduced into it, the inputs of which are connected to the outputs of the code-frequency converter, and the outputs with other inputs of the first and second elements And, the first and second permanent storage devices, respectively inputs connected to the speed controller, and outputs with 2θ inputs for setting the division factors of the first and second frequency dividers, respectively, with a variable division coefficient, a subtracting counter, the input of which of the first is connected to the output of the first element And, and the output through the first register is connected to the input of the initial installation of the second totalizing counter, the initial setting of codes connected to the inputs of the initial setting of the first totalizing and subtracting counters, an adder whose inputs are connected to the outputs of the totalizing counters, and output - to the input of the second register, inputs Recording code of counters and registers connected to the output of the pulse frequency-phase discriminator.